lrs1331 Sharp Microelectronics of the Americas, lrs1331 Datasheet - Page 12

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lrs1331

Manufacturer Part Number
lrs1331
Description
Stacked Chip Flash Memory Sram
Manufacturer
Sharp Microelectronics of the Americas
Datasheet

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LRS1331
Write Cycle (F-WE Controlled)
NOTES:
1. Read timing characteristics during block erase and word write operations are the same as
2. Refer to the ‘Flash Memory Command Definition’ section for valid A
12
Write Cycle Time
F-RP HIGH Recovery to F-WE going to LOW
F-CE Setup to F-WE going LOW
F-WE Pulse Width
F-WP V
F-V
Address Setup to F-WE going HIGH
Data Setup to F-WE going HIGH
Data Hold from F-WE HIGH
Address Hold from F-WE HIGH
F-CE Hold from F-WE HIGH
F-WE Pulse Width HIGH
F-WE HIGH to F-RY/BY going LOW
Write Recovery before Read
F-V
F-WP V
T
during read-only operations. Refer to AC Characteristics for Read Cycle.
A
CCW
CCW
= -25°C to +85°C, V
IH
IH
Setup to F-WE going HIGH
Hold from Valid SRD, F-RY/BY HIGH Z
Setup to F-WE going HIGH
Hold from Valid SRD, F-RY/BY HIGH
PARAMETER
CC
= 2.7 V to 3.6 V
1
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IN
WLWH
SHWH
DVWH
WHDX
WHEH
WHWL
PHWL
VPWH
AVWH
WHAX
WHRL
WHGL
ELWL
AVAV
QVVL
QVSL
and D
IN
for block erase or word write.
MIN.
100
100
90
10
50
50
50
10
30
1
0
0
0
0
0
Stacked Chip (16M Flash & 4M SRAM)
MAX.
100
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
NOTES
2
2

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