ic42s16100 ETC-unknow, ic42s16100 Datasheet - Page 28

• Manufacturer Part Number: ic42s16100
• Description: 512k X 16 Bit X 2 Banks 16-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16100
28
Interval Between Write and Read Commands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
CAS latency = 2, burst length = 4
CAS latency = 3, burst length = 4
COMMAND
COMMAND
CLK
CLK
I/O
I/O
WRITE (CA=A, BANK 0)
WRITE (CA=A, BANK 0)
D
D
WRITE A0
WRITE A0
IN
IN
A0
A0
READ B0
READ B0
t
t
CCD
CCD
READ (CA=B, BANK 0)
READ (CA=B, BANK 0)
HI-Z
D
OUT
HI-Z
B0
The interval (t
clock cycle.
The selected bank must be set to the active state before
executing this command.
D
D
OUT
OUT
B0
B1
D
D
OUT
OUT
CCD
) between command must be at least one
B1
B2
D
D
OUT
OUT
Integrated Circuit Solution Inc.
B2
B3
D
OUT
B3
DR024-0D 06/25/2004
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