ic42s16100 ETC-unknow, ic42s16100 Datasheet - Page 62

• Manufacturer Part Number: ic42s16100
• Description: 512k X 16 Bit X 2 Banks 16-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16100
Read Cycle / Ping Pong Operation (Bank Switching)
62
A0-A9
DQM
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don't Care.
CKE
RAS
CAS
CLK
A10
A11
WE
CS
I/O
t
CKS
t
CS
T0
t
t
t
t
t
t
t
t
CS
CS
CS
AS
AS
AS
t
CKA
CK
CH
<
BANK 0
ACT 0
ROW
ROW
T1
(BANK 0 TO 1)
t
CHI
>
(BANK 0)
(BANK 0)
(BANK 0)
t
t
t
t
t
RRD
RCD
t
t
t
t
RAS
t
AH
AH
CH
CH
CH
AH
RC
T2
t
CL
T3
<
BANK 1
ROW
ROW
ACT1
T4
>
(BANK 1)
t
RCD
<
AUTO PRE
<
COLUMN
READA 0
NO PRE
READ 0
BANK 0
T5
(1)
(BANK 0)
>
>
t
t
CAC
CS
T6
(BANK 1)
(BANK 1)
t
t
RAS
t
QMD
RC
<
<
AUTO PRE
COLUMN
READA 1
READ 1
NO PRE
BANK 1
T7
(1)
>
>
(BANK 1)
t
AC
t
CAC
t
LZ
BANK 0 OR 1
<
BANK 0
PRE 0
T8
D
OUT
t
>
OH
0m
(BANK 0)
(BANK 0)
t
AC
t
RQL
t
RP
T9
D
OUT
t
Integrated Circuit Solution Inc.
OH
0m+1
t
AC
t
BANK 0 OR 1
CH
T10
<
BANK1
PRE 1
D
OUT
t
>
OH
(BANK1)
1m
t
AC
t
RP
<
BANK 0
ACT 0
ROW
ROW
T11
D
OUT
>
t
OH
DR024-0D 06/25/2004
1m+1
(BANK 0)
(BANK 0)
(BANK 0)
t
HZ
t
t
t
RCD
RAS
RC
T12
Undefined
Don’t Care