ic42s16400a ETC-unknow, ic42s16400a Datasheet - Page 27

• Manufacturer Part Number: ic42s16400a
• Description: 1m X 16bit X 4 Banks 64-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16400A
Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid
data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high
at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Integrated Circuit Solution Inc.
DR039-0A 02/19/2004
command
DQM
DQ
CAS latency = 3
CAS latency = 2
Command
DQM
CLK
DQ
T0
Write
D0
Write
D0
T1
D1
D1
RP
from the precharge command. The DQM must be high to mask
T2
D2
D2
T3
D3
D3
T4
PRE
PRE
D4
D4
T5
t
RP
Hi - Z
t
RP
T6
ACT
Hi - Z
T7
Burst lengh = X
ACT
T8
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