ic42s16400a ETC-unknow, ic42s16400a Datasheet - Page 60

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ic42s16400a

Manufacturer Part Number
ic42s16400a
Description
1m X 16bit X 4 Banks 64-mbit Sdram
Manufacturer
ETC-unknow
Datasheet
IC42S16400A
Full Page Read Cycle (2 of 2)
BS1=”L”, Bank C,D = Idle
60
*BS0
DQM
RAS
CAS
ADD
CKE
CLK
A10
WE
DQ
CS
High
Hi-Z
Command
Activate
Bank A
Ra
Ra
T0 T1 T2 T3 T4 T5 T6 T7
t
CK3
Command
Bank A
Read
Ca
Command
Bank B
Activate
Ra
Ra
QAa
QAa+1
The burst counter wraps
from the highest order
page address back to zero
during this time interval
QAa+2 QAa-2 QAa-1
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Command
Bank B
Read
Ca
QAa
Full page burst operation
does not teminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
beginning with the starting
address
QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Burst Length=Full Page, CAS Latency=3
Burst Stop
Command
Precharge
Command
Bank B
Integrated Circuit Solution Inc.
Command
Activate
Bank B
Rb
Rb
DR039-0A 02/19/2004

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