ic42s16400 ETC-unknow, ic42s16400 Datasheet - Page 22

• Manufacturer Part Number: ic42s16400
• Description: 1m X 16bit X 4 Banks 64-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16400
Read / Write Command Interval
Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous
read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminate and the new burst will begin
with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
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Command
Command
CLK
DQ
CLK
DQ
T0
T0
Read A
Write A
QA0
1 cycle
1 cycle
T1
T1
Read B
Write B
QB0
T2
T2
QA0
QB1
T3
T3
QB0
QB2
T4
T4
QB1
QB3
T5
T5
QB2
Integrated Circuit Solution Inc.
Hi-Z_
T6
Burst lengh=4, CAS latency=2
T6
Burst lengh=4, CAS latency=2
QB3
T7
T7
DR034-0E 12/02/2003
Hi-Z_
T8
T8