ic42s32200 ETC-unknow, ic42s32200 Datasheet - Page 9

• Manufacturer Part Number: ic42s32200
• Description: 512k X 32 Bit X 4 Banks 64-mbit Sdram
• Manufacturer: ETC-unknow

IC42S32200
IC42S32200L
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks
for output buffers).A read burst without the auto precharge function may be interrupted by a subsequent Read or Write
command to the same bank or the other active bank before the end of the burst length.It may be interrupted by a
BankPrecharge/PrechargeAll command to the same bank too.The interrupt coming from the Read command can occur on
any clock cycle following a previous Read command (refer to the following figure).
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command.The
DQMs must be asserted (HIGH)at least two clocks prior to the Write command to suppress data-out on the DQ pins.To
guarantee the DQ pins against I/O contention,a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write command (refer to the following three figures).If the data output of the burst read occurs at the
second clock of the burst write,the DQMs must be asserted (HIGH)at least one clock prior to the Write command to avoid
internal bus contention.
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
CAS# latency=2
t CK2 , DQ s
CLK
COMMAND
CAS# latency=3
t CK3 , DQ s
CAS# latency=2
t CK2 , DQ s
CLK
COMMAND
CAS# latency=3
t CK3 , DQ s
Read Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
READ A
Burst Read Operation(Burst Length =4,CAS#Latency =2,3)
T0
READ A
T0
NOP
READ B
T1
T1
T2
DOUT A 0
NOP
DOUT A 0
T2
NOP
DOUT A 1
NOP
T3
DOUT A 0
DOUT B 0
NOP
T3
DOUT A 0
DOUT A 1
DOUT A 2
T4
NOP
DOUT B 0
T4
NOP
DOUT B 1
DOUT A 3
T5
NOP
DOUT A 2
NOP
DOUT B 2
T5
DOUT B 1
DOUT A 3
T6
NOP
NOP
T6
DOUT B 3
DOUT B
2
T7
NOP
T7
NOP
DOUT B 3
NOP
T8
NOP
T8
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