ic42s32800 ETC-unknow, ic42s32800 Datasheet - Page 15

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ic42s32800

Manufacturer Part Number
ic42s32800
Description
2m X 32 Bit X 4 Banks 256-mbit Sdram
Manufacturer
ETC-unknow
Datasheet
IC42S32800
IC42S32800L
Integrated Circuit Solution Inc.
DR046-0B 12/21/2004
7
Mode Register Set command
(RAS#=”L”,CAS#=”L”,WE#=”L”,BS0,1 and A11-A0 =Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM.The Mode Register Set
command programs the values of CAS#latency,Addressing Mode and Burst Length in the Mode register to make
SDRAM useful for a variety of different applications.The default values of the Mode Register after power-up are
undefined;therefore this command must be issued at the power-up sequence.The state of pins BS0,1 and
A11~A0 in the same cycle is the data written to the mode register.One clock cycle is required to complete the write
in the mode register (refer to the following figure).The contents of the mode register can be changed using the
same command and the clock cycle requirements during operation as long as all banks are in the idle state.
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