ic42s32800 ETC-unknow, ic42s32800 Datasheet - Page 23

• Manufacturer Part Number: ic42s32800
• Description: 2m X 32 Bit X 4 Banks 256-mbit Sdram
• Manufacturer: ETC-unknow

IC42S32800
IC42S32800L
6.A.C.Test Conditions
LVTTL Interface
Integrated Circuit Solution Inc.
DR046-0B 12/21/2004
7.
8.
9.
10. Assumed input rise and fall time t
11. Power up Sequence
Reference Level of Output Signals
Output Load
Input Signal Levels
Transition Time (Rise and Fall)of Input Signals
Reference Level of Input Signals
Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope
(1 ns).
t
If clock rising time is longer than 1 ns,(t
If t
should be added to the parameter.
Power up must be performed in the following sequence.
1) Power must be applied to V
and both CKE =”H”and DQM =”H.”The CLK signals must be started at the same
time.
2) After power-up,a pause of 200 seconds minimum is required.Then,it is recom
mended that DQM is held “HIGH”(V
impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
HZ
R
defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
Output
or t
LVTTL A.C. Test Load
F
is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns
Z0=
50Ω
DD
T
30pF
and V
50Ω
1.4V
(t
DD
R
&t
levels)to ensure DQ output is in high
R
DDQ
F
/2 -0.5)ns should be added to the parameter.
)=1 ns
(simultaneously)when all input signals are held “NOP”state
1.4V /1.4V
Reference to the Under Output Load
2.4V /0.4V
1ns
1.4V
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