hb28j128mm3 Renesas Electronics Corporation., hb28j128mm3 Datasheet - Page 38

• Manufacturer Part Number: hb28j128mm3
• Description: Multimediacard 32 Mbyte/64 Mbyte/128 Mbyte/256 Mbyte/512 Mbyte
• Manufacturer: Renesas Electronics Corporation.

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
The host can abort writing at any time, within a multiple block operation, regardless of the its type.
Transaction abort is done by sending the stop transmission command. If a multiple block write with
predefined block count is aborted, the data in the remaining blocks is not defined.
If the card detects an error (e.g. write protect violation, out of range, address misalignment, internal error,
etc.) during a multiple block write operation (both types) it will ignore any further incoming data blocks
and remain in the Receive State. The host must than abort the operation by sending the stop transmission
command. The write error is reported in the response to the stop transmission command.
If the host sends a stop transmission command after the card received the last block of a multiple block
write with a pre-defined number of blocks, it will be responded to as an illegal command, since the card is
no longer in rcv state.
If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not
allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card will detect the block misalignment
error and abort programming before the beginning of the first misaligned block. The card will set the
ADDRESS_ERROR error bit in the status register, and wait (in the Receive-data-State) for a stop
command while ignoring all further data transfer. The write operation will also be aborted if the host tries
to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit.
Programming of the CID and CSD register does not require a previous block length setting. The
transferred data is also CRC protected.
Identification of these erase groups is accomplished with the TAG_ERASE_GROUP commands. A first
command with the starting address is followed by a second command with the final address, and all erase
groups within this range will be selected for erase. The host must adhere to the following command
sequence; TAG_ERASE_GROUP_START, TAG_ERASE_GROUP_END and ERASE. The following
exception conditions are detected by the card: An erase or tag command is received out of sequence. The
card will set the ERASE_SEQUENCE error bit in the status register and reset the whole sequence. An out
of sequence command (except SEND_STATUS) is received. The card will set the ERASE_RESET status
bit in the status register, reset the erase sequence and execute the last command. If the erase range includes
write protected erase groups, they will be left intact and only the non-protected erase groups will be erased.
The WP_ERASE_SKIP status bit in the status register will be set. The address field in the tag commands
is an erase group. The card will ignore all LSB’s below the group size. As described above for block
write, the card will indicate that an erase is in progress by holding DAT low. The actual erase time may be
quite long, and the host may choose to deselect the card using CMD7.
Rev.0.02, Sep.15.2004, page 38 of 89
Erase
transfer state. Stop command is not required at the end of this type of multiple block write, unless
terminated with an error. In order to start a multiple block write with pre-defined block count, the
host must use the SET_BLOCK_COUNT command (CMD23) immediately preceding the
WRITE_MULTIPLE_BLOCK (CMD25) command. Otherwise the card will start an open-ended
multiple block write which can be stopped using the STOP_TRANSMISSION command.
The card will transfer the requested number of data blocks, terminate the transaction and return to
Multiple block write with pre-defined block count