hb28j128mm3 Renesas Electronics Corporation., hb28j128mm3 Datasheet - Page 49

• Manufacturer Part Number: hb28j128mm3
• Description: Multimediacard 32 Mbyte/64 Mbyte/128 Mbyte/256 Mbyte/512 Mbyte
• Manufacturer: Renesas Electronics Corporation.

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
The host command and the card response are clocked out with the rising edge of the host clock. The delay
between host command and card response is N
for host command CMD3:
There is just one Z bit period followed by P bits pushed up by the responding card. The following timing
diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:
The card identification (CMD2) and card operation condition (CMD1) timing are processed in the open-
drain mode. The card response to the host command starts after exactly N
After receiving the last card response, the host can start the next command transmission after at least N
clock cycles. This timing is relevant for any host command.
Rev.0.02, Sep.15.2004, page 49 of 89
Card identification and card operation conditions timing
Last card response - next host command timing
CMD
CMD
CMD
CMD
S T
S T
S T
S T
Timing Response End to Next CMD Start (Data Transfer Mode)
Host command
Host command
Host active
Host active
Host command
content
content
Command Response Timing (Data Transfer Mode)
Host active
Command Response Timing (Identification Mode)
content
Identification Timing (Card Identification Mode)
Card active
content
Response
CRC E Z
CRC E Z Z P
CRC E Z
CRC E Z
CR
N
N
clock cycles. The following timing diagram is relevant
N
* * * * * *
CR
CR
ID
N
* * *
cycles
cycles
* * * * * *
cycles
RC
* * *
cycles
P
Z
Z
S T
S T
S T
Card active
Z
S T
Card active
Response
Card active
Response
content
content
CID or OCR
Host command
ID
content
content
Host active
clock cycles.
CRC E Z Z Z
CRC E Z Z Z
CRC E
Z Z Z
RC