saa4977h NXP Semiconductors, saa4977h Datasheet - Page 15

• Manufacturer Part Number: saa4977h
• Description: Video Processing
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.4
Three identical 10-bit DACs are used to map the 4 : 4 : 4
data to analog levels.
7.5
The SAA4977H contains an embedded 80C51
microprocessor core including a 256 byte RAM and
16 kbyte ROM. The microprocessor runs on a 16 MHz
clock, generated by dividing the 32 MHz display clock by a
factor of 2. For controlling internal registers a host
interface, consisting of a parallel address and data bus, is
built-in, that can be addressed as internal AUX RAM via
MOVX type of instructions.
7.5.1
The I
receive and transmit mode for communication with a
central system microprocessor. The standardized bus
frequencies of both 100 kHz and 400 kHz can be dealt
with.
The I
0110100 R/W.
For a detailed description of the transmission protocol
refer to brochure “The I
number 9398 393 40011) and to Application note “I
register specification of the SAA4977H” (AN98054).
7.5.2
A SNERT interface is built-in, which operates in a master
receive and transmit mode for communication with
peripheral circuits such as the SAA4990H or
SAA4991WP. The SNERT interface replaces the standard
UART interface. In contrast to the 80C51 UART interface
there are additional special function registers and there is
no byte separation time between address and data.
The SNERT interface transforms the parallel data from the
microprocessor into 1 Mbaud SNERT data. The
SNERT-bus consists of three signals: SNCL used as the
serial clock signal and is generated by the SNERT
interface; SNDA used as the bidirectional data line, and
SNRST used as the reset signal and is generated by the
microprocessor to indicate the start of a transmission.
The read or write operation must be set by the
microprocessor. When writing to the bus, 2 bytes are
loaded by the microprocessor: one for the address, the
other for the data.
2000 May 25
Besic
2
2
C-bus interface in the SAA4977H is used in a slave
C-bus slave address of the SAA4977H is
Digital-to-analog conversion
Microprocessor
I
SNERT-
2
C-
BUS
BUS
2
C-bus and how to use it” (order
2
C-bus
15
When reading from the bus, one byte is loaded by the
microprocessor for the address, the received byte is the
data from the addressed SNERT location.
7.5.3
A parallel 8-bit I/O port (P1) is available, where P1.0 is
used as the SNERT reset signal (SNRST), P1.1 to P1.5
can be used for application specific control signals, and
P1.6 and P1.7 are used as I
SDA).
7.5.4
The microprocessor contains an internal Watchdog Timer,
which can be activated by setting the bit 4 in SFR PCON.
Only a synchronous reset will clear this bit. To prevent a
system reset the Watchdog Timer must be reloaded in
time. The Watchdog Timer is incremented every 0.75 ms.
The time interval between the timer’s reloading and the
occurrence of a reset depends on the reloaded 8-bit value.
7.5.5
A reset is accomplished by holding the RST pin HIGH for
at least 0.75 s while the external clock is running.
To guarantee reliable power-up behaviour the reset pulse
must not be performed until V
external clock is running.
7.6
The memory controller provides all necessary acquisition
clock related write signals (WE and RSTW) and display
clock related read signals (RE and IE2) to control one or
two-field memory concepts. Furthermore the drive signals
(HDFL and VDFL) for the horizontal and vertical deflection
power stages are generated. Also a horizontal blanking
pulse BLND is generated which can be used for peripheral
circuits as SAA4990H. The memory controller is
connected to the microprocessor via the host interface.
Start and stop values for all pulses, referring to the
corresponding horizontal or vertical reference signal, are
programmable under control of the internal software.
To allow user access to these control signals via the
I
detailed description of this user interface refer to
Application Note “I
SAA4977H” (AN98054).
2
C-bus a range of subaddresses is reserved; for a
Memory controller
I/O
W
RESET
ATCHDOG
PORTS
2
C-bus register specification of the
T
IMER
2
C-bus signals (SCL and
DD
is stabilized and the
Preliminary specification
SAA4977H