saa4977h NXP Semiconductors, saa4977h Datasheet - Page 17

• Manufacturer Part Number: saa4977h
• Description: Video Processing
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.9
Table 2 Digital input and output bus format
The first phase of the 4 : 1 : 1 YUV dataword is available
on the output bus one SWC clock cycle after the rising
edge of the WE signal. The start position, when the first
phase of the 4 : 1 : 1 YUV data word is expected on the
input bus, can be defined by the internal control signal
HDAV.
The luminance output signal is in 8-bit straight binary
format, whereas U and V output signals are in
2’s complement format. Also the luminance input signal is
expected in 8-bit straight binary format, whereas U and V
input signals are expected in 2’s complement format. The
U and V input signals are inverted if the corresponding
control bit uv_inv is set via the I
7.10
The SAA4977H provides a test mode function which
should not be entered by the customer. If the TRST input
is driven HIGH, different test modes can be selected by
applying a HIGH to the TMS input for a defined number of
LLD clock cycles. To exit the test mode TMS and TRST
must be driven LOW.
2000 May 25
OUTPUT
Besic
UVO7
UVO6
UVO5
UVO4
YO7
YO6
YO5
YO4
YO3
YO2
YO0
Y01
PIN
4 : 1 : 1 I/O interfacing
Test mode operation
U07
U06
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
V07
V06
4 : 1 : 1 FORMAT
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
U05
U04
V05
V04
U03
U02
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
V03
V02
2
C-bus.
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
U01
U00
V01
V00
INPUT
UVI7
UVI6
UVI5
UVI4
PIN
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
17
Preliminary specification
SAA4977H