saa4998h NXP Semiconductors, saa4998h Datasheet - Page 28

• Manufacturer Part Number: saa4998h
• Description: Field And Line Rate Converter With Noise Reduction And Embedded Memory
• Manufacturer: NXP Semiconductors

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PanZoomVec3-X
PanZoomVec3-Y
PanZoomVec4-X
PanZoomVec4-Y
PanZoomVec5-X
PanZoomVec5-Y
PanZoomVec6-X
PanZoomVec6-Y
PanZoomVec7-X
PanZoomVec7-Y
PanZoomVec8-X
PanZoomVec8-Y
EggSliceRgtMSB
EggSliceRgtLSB
EggSliceMixMSB
EggSliceMixLSB
SafeFbLine
EggBinGoodness
LoActCnt
HiActCnt
NullErrSum
NAME
0B6
0B7
0B8
0B9
0BA
0BB
0BC
0BD
0BE
0BF
0AE
0AF
0C0
0C1
0C2
0C3
0C9
0CA
0D3
0D4
0D5
ADDRESS
SNERT
(HEX)
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
WRITE
READ/
(1)
X X X X X X X X pan-zoom vector 2 (8-bit X value)
X X X X X X X X pan-zoom vector 4 (8-bit X value)
X X X X X X X X pan-zoom vector 5 (8-bit X value)
X X X X X X X X pan-zoom vector 6 (8-bit X value)
X X X X X X X X pan-zoom vector 7 (8-bit X value)
X X X X X X X X pan-zoom vector 8 (8-bit X value)
X X X X X X X X result of right pixels egg-slice detector (15 to 8)
X X X X X X X X result of right pixels egg-slice detector (7 to 0)
X X X X X X X X result of mixed pixels egg-slice detector (15 to 8)
X X X X X X X X result of mixed pixels egg-slice detector (7 to 0)
X X X X X X X X reference line number (divided by two) at which the upconverter goes
X X X X X X X X Goodness of the four egg-slice sections, from top to bottom, 2 bits per
X X X X X X X X number of blocks having low activity
X X X X X X X X number of blocks having high activity
X X X X X X X X sum of errors for the null candidate over the complete field; when no
7 6 5 4 3 2 1 0
X X X X X X X pan-zoom vector 3 (7-bit Y value)
X X X X X X X pan-zoom vector 4 (7-bit Y value)
X X X X X X X pan-zoom vector 5 (7-bit Y value)
X X X X X X X pan-zoom vector 6 (7-bit Y value)
X X X X X X X pan-zoom vector 7 (7-bit Y value)
X X X X X X X pan-zoom vector 8 (7-bit Y value)
into protection mode
section. Each section is represented with 2 bits in this register, where
bits 0 and 1 represent the top section and bits 6 and 7 represent the
lowest of the 4 sections. Each pair of bits indicate
00 = (ESR >
10 = (
null candidate is selected a value of FFH will be read
1
4
ESM < ESR
3
4
ESM), 01 = (
1
2
ESM), 11 = (ESR
DESCRIPTION
1
2
ESM < ESR
(2)
3
1
4
4
ESM),
ESM).