mt8htf12864az Micron Semiconductor Products, mt8htf12864az Datasheet - Page 4

• Manufacturer Part Number: mt8htf12864az
• Description: 1gb X64, Sr 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 5:
PDF: 09005aef83b94f21/Source: 09005aef83b94f31
HTF8C128x64AZ.fm - Rev. A 8/09 EN
RAS#, CAS#,
DQS#[7:0]
V
DQ[63:0]
DQS[7:0]
Symbol
CK#[2:0]
DM[7:0]
BA[2:0]
A[13:0]
CK[2:0]
SA[2:0]
V
DD
ODT0
CKE0
WE#
SDA
V
DDSPD
S0#
SCL
V
NC
/V
REF
SS
DDQ
Pin Descriptions
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
–
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA[2:0]) or all device banks (A10 HIGH). The address inputs also provide the op-
code during a LOAD MODE command.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR, EMR1,
EMR2, and EMR3), is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry
and clocks on the DDR2 SDRAM.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH, along with that input data, during a write access. DM is sampled on both
edges of DQS. Although the DM pins are input-only, DM loading is designed to match that of
the DQ and DQS pins.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: These pins are used to configure the SPD EEPROM address range on
the I
Serial clock for SPD EEPROM: SCL is used to synchronize communication to and from the
SPD EEPROM.
Data input/output: Bidirectional data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data. DQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the SPD EEPROM on the module on the I
Power supply: 1.8V ±0.1V. The component V
SPD EEPROM power supply: +1.7V to +3.6V.
Reference voltage: V
Ground.
No connect: These pins are not connected on the module.
2
C bus.
DD
/2.
4
1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Description
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
C bus.
DD
Pin Assignments and Descriptions
and V
DDQ
are connected to the module V
©2003 Micron Technology, Inc. All rights reserved.
DD
.