mt8htf12864az Micron Semiconductor Products, mt8htf12864az Datasheet - Page 9

• Manufacturer Part Number: mt8htf12864az
• Description: 1gb X64, Sr 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

I
Table 8:
PDF: 09005aef83b94f21/Source: 09005aef83b94f31
HTF8C128x64AZ.fm - Rev. A 8/09 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus inputs
are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
t
commands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current (Standard): CK and CK# at 0V; CKE ≤ 0.2V; Other control
and address bus inputs are floating; Data bus inputs are floating
Self refresh current (Low Power): CK and CK# at 0V; CKE ≤ 0.2V; Other
control and address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
DD
RC =
RCD =
CK =
RAS =
RP =
RAS =
CK =
Specifications
t
t
t
t
RP (I
RC (I
CK (I
CK (I
t
t
OUT
OUT
t
RAS MAX (I
RAS MAX (I
RCD (I
DD
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
DDR2 I
Values are shown for the MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus
),
DD
t
t
RAS =
RC =
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
DD
t
t
),
),
CK =
DD
RC (I
t
RAS MIN (I
t
t
DD
RP =
RP =
t
CK =
Specifications and Conditions – 1GB
), AL = 0;
DD
t
CK (I
),
t
t
RP (I
RP (I
t
CK (I
t
RRD =
DD
DD
DD
DD
),
DD
DD
t
DD
); CKE is HIGH, S# is HIGH between valid
CK =
t
); CKE is HIGH, S# is HIGH between valid
); CKE is HIGH, S# is HIGH between valid
RC =
), AL = 0;
), AL =
); REFRESH command at every
t
RRD (I
t
CK (I
t
RC (I
t
DD
RCD (I
DD
t
),
DD
CK =
),
t
t
DD4W
),
RCD =
CK =
t
t
DD
RAS =
t
CK =
t
RAS =
CK =
t
CK (I
) - 1 ×
t
CK (I
t
t
t
RCD (I
OUT
CK (I
CK =
t
t
DD
t
CK (I
RAS MAX (I
t
CK =
RAS MIN (I
9
t
DD
),
CK (I
1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
= 0mA; BL = 4,
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
DD
t
),
DD
DD
CK (I
t
),
CK (I
DD
); CKE is
); CKE is
);
t
DD
RFC (I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
DD
);
);
),
),
DD
)
Symbol
I
I
I
I
I
I
I
I
I
DD3PF
DD3PS
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
I
DD2P
DD4R
DD6L
DD0
DD1
DD5
DD6
DD7
Electrical Specifications
-1GA
1040
1680
1680
2120
3400
920
480
480
400
560
56
80
56
24
©2003 Micron Technology, Inc. All rights reserved.
-80E/
1280
1280
1880
2680
-800
720
880
400
400
320
480
56
80
56
24
-667
1080
1080
1720
2240
680
800
320
320
240
440
56
80
56
24
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA