mt16vddf6464hy-40b Micron Semiconductor Products, mt16vddf6464hy-40b Datasheet - Page 4

• Manufacturer Part Number: mt16vddf6464hy-40b
• Description: 512mb, 1gb X64, Dr Pc3200 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

Table 5:
PDF: 09005aef80b57837/Source: 09005aef80b577fa
DDAF16C64_128x64H.fm - Rev. E 10/06 EN
DQS0–DQS7
CKE0, CKE1
DQ0–DQ63
CAS#,RAS#
DM0–DM7
CK0, CK0#
CK1, CK1#
BA0, BA1
SA0–SA2
Symbol
S0#, S1#
A0–A12
Vdd
WE#,
SDA
V
V
SCL
V
REF
DD
SS
SPD
Pin Descriptions
Output
Output
Output
Supply
Supply
Supply
Supply
Input/
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK, and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers
and output drivers. Taking CKE LOW provides precharge power-down and SELF REFRESH
operations (all device banks idle), or active power-down (row ACTIVE in any device bank).
CKE is synchronous for power-down entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained
HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during power-down. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after V
and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input
only.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when S# is registered HIGH. S# is considered part of the
command code.
Bank address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied.
Address inputs: Provide the row address for ACTIVE commands, and the column address and
auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-
code during a MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer
to and from the module.
Presence-Detect address inputs: These pins are used to configure the presence-detect device.
Data write mask. DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM
lines do not affect READ operation.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data
into and out of the presence-detect portion of the module.
Data strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ
data, centered in WRITE data. Used to capture data.
Data I/Os: Data bus.
SSTL_2 reference voltage.
Power supply: +2.6V ±0.1V.
Ground.
Serial EEPROM positive power supply: +2.3V to +3.6V
512MB, 1GB: (x64, DR) PC3200 200-Pin DDR SODIMM
4
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2004 Micron Technology, Inc. All rights reserved.
DD
is applied