k9f1208u0c Samsung Semiconductor, Inc., k9f1208u0c Datasheet
k9f1208u0c
Available stocks
Related parts for k9f1208u0c
k9f1208u0c Summary of contents
Page 1
... K9F1208U0C K9F1208R0C K9F1208B0C INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...
Page 2
... K9F1208U0C K9F1208R0C K9F1208B0C Document Title 64M x 8 Bits NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 0.1 2.7V part is added 0.2 Address of Read 2 is changed (A 0.3 1. Add tRPS/tRCS/tREAS parameter for status read 2. Add nWP timing guide 0.4 1. Change from tRPS/tRCS/tREAS to tRPB/tRCB/tREAB parameter for 1.8V device busy state ...
Page 3
... K9F1208U0C-P 2.7V ~ 3.6V K9F1208U0C-J FEATURES • Voltage Supply - 1.8V Device(K9F1208R0C) : 1.65V ~ 1.95V - 2.7V Device(K9F1208B0C) : 2.5V ~ 2.9V - 3.3V Device(K9F1208U0C) : 2.7V ~ 3.6V • Organization - Memory Cell Array : (64M + 2M) x 8bits - Data Register : (512 + 16) x 8bits • Automatic Program and Erase - Page Program : (512 + 16) x 8bits - Block Erase : (16K + 512)Bytes • Page Read Operation ...
Page 4
... K9F1208U0C K9F1208R0C K9F1208B0C PIN CONFIGURATION (TSOP1) N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220AF #1 #24 0~8° 0.45~0.75 0.018~0.030 K9F1208X0C-PCB0/PIB0 48 47 ...
Page 5
... K9F1208U0C K9F1208R0C K9F1208B0C PIN CONFIGURATION (FBGA) N.C N.C N N.C N.C N.C K9F1208X0C-JCB0/JIB0 N.C N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE I/ Vcc NC I/O1 NC VccQ I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C N.C Top View 5 FLASH MEMORY ...
Page 6
... K9F1208U0C K9F1208R0C K9F1208B0C 63-Ball FBGA (measured in millimeters) Top View 8.50 ±0.10 #A1 0.10MAX Bottom View #A1 INDEX MARK(OPTIONAL) 8.50 ±0.10 0. 7.20 0. 4.00 0. (Datum (Datum 63-∅0.45 ±0.05 ∅ 0. 2.00 Side View 13.00 ±0.10 0.45 ±0.05 6 FLASH MEMORY ...
Page 7
... K9F1208U0C K9F1208R0C K9F1208B0C PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
Page 8
... K9F1208U0C K9F1208R0C K9F1208B0C Figure 1. K9F1208X0C FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage Generator WE CLE ALE Figure 2. K9F1208X0C ARRAY ORGANIZATION 128K Pages 1st half Page Register ...
Page 9
... K9F1208U0C K9F1208R0C K9F1208B0C Product Introduction The K9F1208X0C is a 528Mbits(553,648,218 bits) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col- umns are located from column address of 512 to 527. A 528-bytes data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
Page 10
... V Input Low Voltage, All inputs IL K9F1208R0C K9F1208B0C: I Output High Voltage Level OH K9F1208U0C: I K9F1208R0C K9F1208B0C: I Output Low Voltage Level OL K9F1208U0C (R/B) V Output Low Current(R/ Notes : 1. Typical values are measured at Vcc=3.3V, TA=25°C. And not 100% tested. Symbol 1.8V Device 2.45 ...
Page 11
... K9F1208X0C-XIB0:TA=-40 to 85°C). Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels K9F1208R0C:Output Load (Vcc:1.8V +/-10%) K9F1208B0C:Output Load (Vcc:2.7V +/-10%) K9F1208U0C:Output Load (Vcc:3.3V +/-10%) K9F1208U0C:Output Load (Vcc:3.0V +/-10%) CAPACITANCE (TA=25°C, VCC=1.8V/2.7V/3.3V, f=1.0MHz) Item Symbol Input/Output Capacitance C Input Capacitance C NOTE : Capacitance is periodically sampled and not 100% tested ...
Page 12
... K9F1208U0C K9F1208R0C K9F1208B0C Program / Erase Characteristics Parameter Program Time Number of Partial Program Cycles in the Same Page Block Erase Time NOTE NOTE: 1.Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT ...
Page 13
... K9F1208U0C K9F1208R0C K9F1208B0C AC CHARACTERISTICS FOR OPERATION Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z CE High to ALE or CLE Don’t Care ...
Page 14
... K9F1208U0C K9F1208R0C K9F1208B0C NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
Page 15
... K9F1208U0C K9F1208R0C K9F1208B0C NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done ...
Page 16
... K9F1208U0C K9F1208R0C K9F1208B0C NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...
Page 17
... K9F1208U0C K9F1208R0C K9F1208B0C Pointer Operation of K9F1208X0C Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...
Page 18
... K9F1208U0C K9F1208R0C K9F1208B0C System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
Page 19
... K9F1208U0C K9F1208R0C K9F1208B0C * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle t CLS CLE ALS ALE t I CLH CLS ALS ALH Command ALH ALH t t ALS ...
Page 20
... K9F1208U0C K9F1208R0C K9F1208B0C * Input Data Latch Cycle CLE ALE t ALS I/Ox DIN 0 * Serial access Cycle after Read CE t REA RE I/ R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested ...
Page 21
... K9F1208U0C K9F1208R0C K9F1208B0C Status Read Cycle (During Ready State) CLE I/O X R/B Status Read Cycle (During Busy State) CLE I/O X R/B t CLR t CLS t CLH CEA t WHR 70h/7Ah t CLR t CLS t CLH CEA t WHR ...
Page 22
... Address Address R/B On K9F1208X0C-P CE must be held low during Dout N+1 Dout N+2 A Dout Busy NOTES : 1) is only valid on K9F1208X0C-P On K9F1208U0C-P CE must be held low during Dout N Dout N Busy 22 FLASH MEMORY 1) t CEH ...
Page 23
... K9F1208U0C K9F1208R0C K9F1208B0C Read2 Operation (Read One Page) CLE CE WE ALE RE I/O 50h R/B M Address Sequential Row Read Operation CLE CE WE ALE RE 00h I R Valid Address ...
Page 24
... K9F1208U0C K9F1208R0C K9F1208B0C Page Program Operation CLE ALE RE I/O 80h Sequential Data Column Page(Row) Input Command Address R/B Block Erase Operation (Erase One Block) CLE ALE RE I/O 60h Page(Row) Address R/B Erase Setup Command ...
Page 25
... K9F1208U0C K9F1208R0C K9F1208B0C Read ID Operation CLE CE WE ALE RE I/O 90h X Read ID Command Address. 1cycle ID Defintition Table Access command = 90H Value st 1 Byte ECh Maker Code nd 2 Byte 76h Device Code rd 5Ah Don’t support Copy Back Operation 3 Byte 3Fh Don’t support Multi Plane Operation ...
Page 26
... K9F1208U0C K9F1208R0C K9F1208B0C Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis- ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. ...
Page 27
... K9F1208U0C K9F1208R0C K9F1208B0C Figure 7. Read1 Operation CLE CE WE ALE R/B RE 00h Start Add.(4Cycle) I & NOTE : 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. On K9F1208X0C-P CE must be held low during tR ...
Page 28
... K9F1208U0C K9F1208R0C K9F1208B0C Figure 8. Read2 Operation CLE CE WE ALE R/B RE 50h I/O Start Add.(4Cycle & Fixed "Low" K9F1208X0C-P CE must be held low during Main array Data Field Spare Field 28 FLASH MEMORY Data Output(Sequential) Spare Field ...
Page 29
... K9F1208U0C K9F1208R0C K9F1208B0C Figure 9. Sequential Row Read1 Operation R/B I/O X 00h Start Add.(4Cycle) 01h & 00h Command) 1st half array Block Data Field The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation must be terminated by bringing CE high ...
Page 30
... K9F1208U0C K9F1208R0C K9F1208B0C PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 byte single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array ...
Page 31
... K9F1208U0C K9F1208R0C K9F1208B0C BLOCK PROTECT Each block is protected from programming and erasing, controlled by the protect flag written in a specified area in the block. Block Proctect opreation is initiated by wirting 4xh-80h-10h to the command register along with four address cycles. Only address valid while fixed as 00h ...
Page 32
... K9F1208U0C K9F1208R0C K9F1208B0C Figure 14. Read Block Status CLE ALE WE I/O 00h A0~7 : 00h, A9~ fixed, A14~ 4095 RE R/B Table 3. Status Register Definition for 7Ah Command I/O Status I/O 0 Programming Protect I/O 1 Erasing Protect I/O 2 Not use I/O 3 Not Use I/O 4 Not Use I/O 5 Not Use I/O 6 Device Operation ...
Page 33
... Busy : "0" Write Protect Write Protect Protected : "0" t CEA WHR t REA Device ECh Code Maker code Device K9F1208R0C K9F1208B0C K9F1208U0C 33 FLASH MEMORY Definition Fail : "1" Ready : "1" Not Protected : "1" 5Ah 3Fh Device Code 36h 76h 76h ...
Page 34
... K9F1208U0C K9F1208R0C K9F1208B0C RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...
Page 35
... K9F1208U0C K9F1208R0C K9F1208B0C READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
Page 36
... K9F1208U0C K9F1208R0C K9F1208B0C 300n 200n 100n 300n 200n 100n 300n 200n 100n Rp value guidance V CC Rp(min, 1.8V part Rp(min, 2.7V part Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. L Rp(max) is determined by maximum permissible limit of tr ° ...
Page 37
... K9F1208U0C K9F1208R0C K9F1208B0C Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.7V device), 2V(3.3V device). WP pin provides hard- ware protection and is recommended to be kept at V required before internal circuit gets ready for any command sequences as shown in Figure 18 ...
Page 38
... K9F1208U0C K9F1208R0C K9F1208B0C WP AC Timing guide Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows: Figure A-1. Program Operation 1. Enable Mode WE I/O WP R/B 2. Disable Mode WE I/O WP R/B Figure A-2. Erase Operation 1. Enable Mode WE I/O WP R/B 2. Disable Mode WE I/O WP ...