m393t5663cza-cf7/e6 Samsung Semiconductor, Inc., m393t5663cza-cf7/e6 Datasheet
m393t5663cza-cf7/e6
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m393t5663cza-cf7/e6 Summary of contents
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... RDIMM DDR2 Registered SDRAM MODULE 240pin Registered Module based on 1Gb C-die 60FBGA & 63FBGA with Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... AC Input Test Conditions 10.0 IDD Specification Parameters Definition ............................................................................... 14 11.0 Operating Current Table ..........................................................................................................15 11.1 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module 11.2 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module 11.3 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module 11.4 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module 11.5 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module 11.6 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module 11.7 M393T1G60CJA : 8GB(512Mx4 *36) Module 11 ...
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RDIMM Revision History Revision Month Year 1.0 March 2007 1.1 April 2007 1.2 June 2007 1.3 July 2007 1.4 November 2007 History - Initial Release - Add the 2GB Registered DIMM Product - Added IDD values for DDR2-800 - Corrected ...
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... RDIMM 1.0 DDR2 Registered DIMM Ordering Information Part Number Density Organization M393T5663CZ3-CD5/CC 2GB M393T5663CZA-CF7/E6 2GB M393T5660CZ3-CD5/CC 2GB M393T5660CZA-CF7/E6 2GB M393T5160CZ3-CD5/CC 4GB M393T5160CZA-CF7/E6 4GB M392T5160CJA-CF7/E6 4GB M393T1G60CJA-CE6/D5 8GB Note : 1. “Z” of Part number(11th digit) stand for Lead-free products. and "J" of Part number(11th digit) stand for dual-die package products. ...
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... RESET (Pin 18) is connected to both OE of PLL and Reset of register. 2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs) 3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity. ...
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RDIMM 6.0 Input/Output Function Description Symbol Type Input CK0 Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. Input CK0 Negative line of the differential pair of system clock inputs that drives ...
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... RDQS SA0 SA1 SA2 D17 Note : 1. DQ-to-I/O wiring may be changed per nibble. 2. Unless otherwise noted, resister values are 22 Ohms 3. RS0 and RS1 alternate between the back and front sides of the DIMM Signals for Address and Command Parity Function (M393T5663CZA ...
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... RDIMM 7.2 2GB, 256Mx72 Module - M393T5660CZ3/M393T5660CZA (populated as 1 rank of x4 DDR2 SDRAMs) VSS RS0 DQS0 DQS0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQS1 DQS1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQS2 DQS2 DM CS DQS DQS DQ16 I/O 0 DQ17 I ...
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... RDIMM 7.3 4GB, 512MBx72 Module - M393T5160CZ3/M393T5160CZA (populated as 2 rank of x4 DDR2 SDRAMs) VSS RS1 RS0 DQS0 DQS0 DM CS DQS DQS DM/ CS DQS DQS DQ0 I/O 0 I/O 0 DQ1 I D18 DQ2 I/O 2 I/O 2 DQ3 I/O 3 I/O 3 DQS1 DQS1 DM CS DQS DQS DM/ CS DQS DQS DQ8 I/O 0 I/O 0 DQ9 ...
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... RDIMM 7.4 4GB, 512MBx72 Module - M392T5160CJ (populated as 2 rank of x4 DDR2 SDRAMs) VSS RS1 RS0 DQS0 DQS0 DM CS DQS DQS DM/ CS DQS DQS DQ0 I/O 0 I/O 0 DQ1 I D18 DQ2 I/O 2 I/O 2 DQ3 I/O 3 I/O 3 DQS1 DQS1 DM CS DQS DQS DM/ CS DQS DQS DQ8 I/O 0 I/O 0 DQ9 ...
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... RDIMM 7.5 8GB, 1GBx72 Module - M393T1G60CJA (populated as 4 rank of x4 DDR2 SDRAMs) RODT0 RODT1 RCKE0 RCKE1 RS1 RS3 RS0 RS2 22 : DQS0 DQS DQS DQS0 DQS DQS DQ3~0 DQ3~0 DQ3 DQS1 DQS DQS DQS1 DQS DQS DQ11~8 DQ3~0 DQ3 DQS2 DQS ...
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RDIMM 8.0 Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL DDL Voltage on ...
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RDIMM 9.2 Operating Temperature Condition Symbol Parameter TOPER Operating Temperature Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...
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RDIMM 10.0 IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is ...
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... IDD4R 2115 IDD5B 2115 IDD6* 270 IDD7 3150 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 11.2 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module - considering Register and PLL current value Symbol F7(800@CL=6) IDD0 1950 IDD1 2120 IDD2P ...
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... IDD4R 3670 IDD5B 4160 IDD6* 270 IDD7 6430 */IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. E6(667@CL=5) D5(533@CL=4) 1530 1440 1710 1620 270 270 810 ...
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... IDD4R 4870 IDD5B 5450 IDD6* 540 IDD7 8010 */IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. E6(667@CL=5) D5(533@CL=4) 2340 2250 2520 2430 540 540 1620 ...
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... IDD4R 5800 IDD5B 6670 IDD6* 1080 IDD7 8920 */IDD6 = DRAM current + standby current of PLL and Register ** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. D5(533@CL=4) CC(400@CL=3) 3870 3600 4050 3780 1080 1080 3240 ...
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... Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin Speed DDR2-800(F7) Bin (CL - tRCD - tRP) Parameter min tCK, CL=3 - tCK, CL=4 3.75 tCK, CL=5 3 tCK, CL=6 2.5 tRCD 15 tRP 15 tRC 60 tRAS 45 70000 Min Max Min Max M393T5663CZ3 M393T5660CZ3 M393T5663CZA M393T5660CZA - 1.8V + 0.1V) DD Symbol 256Mb tRFC 75 0qCdT d 85qC 7.8 CASE tREFI 85qC T d 95qC 3 ...
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RDIMM 13.3 Timing Parameters by Speed Grade Symbol Parameter DQ output access time from CK/CK tAC DQS output access time from CK/CK tDQSCK CK high-level width tCH CK low-level width tCL CK half period tHP Clock cycle time, CL=x tCK ...
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RDIMM Symbol Parameter Exit active power down to read command tXARD Exit active power down to read command tXARDS (slow exit, lower power) CKE minimum pulse width tCKE (high and low pulse width) ODT turn-on delay tAOND ODT turn-on tAON ...
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... RDIMM 14.0 Physical Dimensions : 14.1 128Mbx8/256Mbx4 based 256Mx72 Module (2/1 Ranks) - M393T5663CZ3/M393T5663CZA/M393T5660CZ3/M393T5660CZA 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 128M x8 / 256M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T1G084QC / K4T1G044QC 133.35 PLL A B 55.00 4.00 0.80±0.05 3.80 0.20 1.00 Detail DDR2 SDRAM Units : Millimeters 4.00 30.00 1.0 max 1.27 ± 0.10 3.00 4.00 Rev. 1.4 November 2007 ...
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... RDIMM 14.2 256Mbx4 based 512Mx72 Module (2 Ranks) - M393T5160CZ3 / M393T5160CZA 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 256M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T1G044QC 133.35 PLL A B 55.00 4.00 0.80±0.05 3.80 0.20 1.00 Detail DDR2 SDRAM Units : Millimeters 4.00 30.00 1.0 max 1.27 ± 0.10 3.00 4.00 Rev. 1.4 November 2007 ...
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... RDIMM 14.3 DDP 512Mbx4 based 512Mx72 Module (2 Ranks) - M392T5160CJA 5.175 63 5.00 4.00 2.50 1.50±0.10 Detail A The used device is DDP 512M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T2G044QC 133.35 128.95 55 123 A B 133.35 4.00 0.80±0.05 3.80 0.20 1.00 Detail DDR2 SDRAM Units : Millimeters 2x 3.00 MIN 2.20 4.17 1.4 max 1.27 ± 0.10 Rev. 1.4 November 2007 ...
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... RDIMM 14.4 DDP 512Mbx4 based 1Gx72 Module (4 Ranks) - M393T1G60CJA 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 256M x4 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T1G044QC 133. 55.00 4.00 0.80±0.05 3.80 0.20 1.00 Detail DDR2 SDRAM Units : Millimeters 4.17 30.00 1.0 max 1.27 ± 0.10 3.00 4.00 Rev. 1.4 November 2007 ...
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RDIMM 15.0 240 Pin DDR2 Registered DIMM Clock Topology CK0 120 ohms CK0 120 ohms C Note: 1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set ...