m393t5663cza-cf7/e6 Samsung Semiconductor, Inc., m393t5663cza-cf7/e6 Datasheet - Page 2

• Manufacturer Part Number: m393t5663cza-cf7/e6
• Description: Ddr2 Registered Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

RDIMM
Table of Contents
1.0 DDR2 Registered DIMM Ordering Information ..........................................................................4
2.0 Features ........................................................................................................................................4
3.0 Address Configuration ................................................................................................................4
4.0 Pin Configurations (Front side/Back side) ................................................................................5
5.0Pin Description .............................................................................................................................5
6.0 Input/Output Function Description ............................................................................................6
7.0 Functional Block Diagram ...........................................................................................................7
8.0 Absolute Maximum DC Ratings ................................................................................................12
9.0 AC & DC Operating Conditions ................................................................................................12
10.0 IDD Specification Parameters Definition ............................................................................... 14
11.0 Operating Current Table ..........................................................................................................15
12.0 Input/Output Capacitance .......................................................................................................19
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 .....................................19
14.0 Physical Dimensions : .............................................................................................................22
15.0 240 Pin DDR2 Registered DIMM Clock Topology .................................................................26
7.1 2GB, 256Mx72 Module - M393T5663CZ3/M393T5663CZA
7.2 2GB, 256Mx72 Module - M393T5660CZ3/M393T5660CZA
7.3 4GB, 512MBx72 Module - M393T5160CZ3/M393T5160CZA
7.4 4GB, 512MBx72 Module - M392T5160CJ
7.5 8GB, 1GBx72 Module - M393T1G60CJA
9.1 Recommended DC Operating Conditions (SSTL - 1.8)
9.2 Operating Temperature Condition
9.3 Input DC Logic Level
9.4 Input AC Logic Level
9.5 AC Input Test Conditions
11.1 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module
11.2 M393T5663CZ3 / M393T5663CZA : 2GB(128Mx8 *18) Module
11.3 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module
11.4 M393T5660CZ3 / M393T5660CZA : 2GB(256Mx4 *18) Module
11.5 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module
11.6 M393T5160CZ3 / M393T5160CZA / M392T5160CJA : 4GB(256Mx4 *36 / 512Mx4 *18) Module
11.7 M393T1G60CJA : 8GB(512Mx4 *36) Module
11.8 M393T1G60CJA : 8GB(512Mx4 *36) Module
13.1 Refresh Parameters by Device Density
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
13.3 Timing Parameters by Speed Grade
14.1 128Mbx8/256Mbx4 based 256Mx72 Module (2/1 Ranks)
14.2 256Mbx4 based 512Mx72 Module (2 Ranks)
14.3 DDP 512Mbx4 based 512Mx72 Module (2 Ranks)
14.4 DDP 512Mbx4 based 1Gx72 Module (4 Ranks)
..................................................................................................................13
..................................................................................................................13
............................................................................................................13
................................................................................................13
..........................................................................................20
........................................................................................ 11
........................................................................................10
......................................................................................19
.................................................................................18
................................................................................18
................................................................................23
2 of 26
............................................................................25
........................................................................24
.....................................................................12
...................................................................7
...................................................................8
................................................................22
.................................................................9
.........................................................15
.........................................................15
.........................................................16
.........................................................16
...........................................19
Rev. 1.4 November 2007
DDR2 SDRAM
..............17
..............17