m393t5663cza-cf7/e6 Samsung Semiconductor, Inc., m393t5663cza-cf7/e6 Datasheet - Page 20

• Manufacturer Part Number: m393t5663cza-cf7/e6
• Description: Ddr2 Registered Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

RDIMM
13.3 Timing Parameters by Speed Grade
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for
each input
DQ and DM input pulse width for each input tDIPW
Data-out high-impedance time from CK/CK tHZ
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ
signals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated
clock edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB
page size products
Active to active command period for 2KB
page size products
Four Activate Window for 1KB page size
products
Four Activate Window for 2KB page size
products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Internal read to precharge command delay tRTP
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-
read command
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tIPW
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tXSNR
tXSRD
tXP
Symbol
tRFC + 10
min(tCL,t
WR+tRP
tAC min
2* tAC
- 0.25
tHP -
tQHS
2500
min
- 400
- 350
0.45
0.45
0.35
0.35
CH)
125
0.35
min
250
175
200
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
50
0.6
10
35
45
7.5
15
2
2
DDR2-800
x
x
x
2
tAC max
tAC max
tAC max
max
8000
0.55
0.55
0.25
200
300
400
350
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
20 of 26
tRFC + 10
WR+tRP
min(tCL,
tAC min
2*tAC
tHP -
tQHS
-0.25
3000
min
-400
0.45
0.45
tCH)
0.35
0.35
0.35
37.5
-450
175
100
0.35
min
275
200
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
7.5
10
50
7.5
15
2
2
x
DDR2-667
x
x
2
tAC max
tAC max
tAC max 2* tACmin tAC max 2* tACmin
max
+400
8000
0.55
0.55
0.25
+450
240
0.6
1.1
0.6
340
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
tRFC + 10
WR+tRP
min(tCL,
tAC min
tHP -
tQHS
-0.25
3750
min
0.45
0.45
tCH)
0.35
0.35
37.5
-500
-450
225
100
0.35
375
250
200
0.6
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
7.5
10
50
15
2
2
2
x
DDR2-533
x
x
tAC max
tAC max
max
+500
+450
8000
0.55
0.55
0.25
300
400
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Rev. 1.4 November 2007
tRFC + 10
WR+tRP
min(tCL,
tAC min
tHP -
tQHS
-0.25
5000
min
-600
-500
0.45
0.45
tCH)
0.35
0.35
0.35
37.5
275
150
0.35
475
350
200
0.6
0.2
0.2
0.4
0.9
0.4
7.5
7.5
10
50
15
10
2
2
2
x
DDR2-400
x
x
DDR2 SDRAM
tAC max
tAC max
tAC max
max
+600
+500
0.55
0.55
8000
0.25
350
450
0.6
1.1
0.6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
Notes