m470l3223dt0 Samsung Semiconductor, Inc., m470l3223dt0 Datasheet - Page 13

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m470l3223dt0

Manufacturer Part Number
m470l3223dt0
Description
256mb Ddr Sdram Module
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
AC Timming Parameters & Specifications
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
Write Preamble
Write Postamble
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup/hold time
(fast slew rate)
Address and Control Input setup/hold time
(slow slew rate)
DQ and DM input setup time
DQ and DM input hold time
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
M470L3223DT0
Parameter
CL=2.0
CL=2.5
tDQSCK
tWPRES
Symbol
tWPRE
tDQSQ
tDQSS
tWPST
tDQSH
tRPRE
tRPST
tDQSL
tIS/tIH
tIS/tIH
tWTR
tRCD
tRRD
tRFC
tRAS
tDSS
tDSH
tWR
tRC
tCH
tDH
tRP
tCK
tCL
tAC
tDS
tHZ
tLZ
-TCB3(DDR333)
(These AC charicteristics were tested on the Component)
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.45
0.45
Min
-0.6
-0.7
-0.7
-0.7
7.5
0.9
0.4
0.4
0.2
0.2
0.8
60
72
42
18
18
12
15
1
6
0
-
Max
0.55
0.55
+0.6
+0.7
0.45
1.25
+0.7
+0.7
70K
1.1
0.6
0.6
12
12
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
Note
4
4
4
2
3
Rev. 0.0 Dec. 2001

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