m470l3223dt0 Samsung Semiconductor, Inc., m470l3223dt0 Datasheet - Page 14

• Manufacturer Part Number: m470l3223dt0
• Description: 256mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
4. For registered DINNs, t
5. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
M470L3223DT0
Mode register set cycle time
Control & Address input pulse width
(for each input)
DQ & DM input pulse width(for each input)
Exit self refresh to non read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Auto Precharge Write recovery +
Precharge time
but system performance (bus turnaround) will degrade accordingly.
jitter due to crosstalk (t
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
Parameter
CL
JIT
64Mb, 128Mb
256Mb
(crosstalk)
and t
CH
are
) on the DIMM.
45% of the period including both the half period jitter (t
Symbol
tXSNR
tXSRD
tDIPW
tMRD
tREFI
tQHS
tRAP
tIPW
tDAL
tQH
tHP
(tWR/tCK) +
or tCHmin
tHP-tQHS
tRAS min
(tRP/tCK)
tRCD or
tCLmin
-TCB3(DDR333)
1.75
15.6
Min
200
2.2
7.8
12
75
Max
0.55
-
-
Unit
tCK
tCK
ns
ns
ns
ns
us
us
ns
ns
ns
ns
Note
1
1
4
3
5
JIT(HP)
) of the PLL and the half period
Rev. 0.0 Dec. 2001