m470l3223dt0 Samsung Semiconductor, Inc., m470l3223dt0 Datasheet - Page 7

• Manufacturer Part Number: m470l3223dt0
• Description: 256mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
2. Timing patterns
DDR SDRAM I
M470L3223DT0
* Module
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR333(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=10*tCK, tRAS=7*tCK
IDD6
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every burst
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
Symbol
IDD4W
IDD2Q
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD7A
IDD0
IDD1
IDD5
Low power
I
Normal
DD
was calculated on the basis of component
DD
B3(DDR333@CL=2.5)
spec table
1360
1360
1440
2600
720
960
200
160
280
440
24
24
12
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
1120
1120
1320
2240
640
880
160
144
240
360
24
24
12
I
DD
and can be differently measured according to DQ loading cap.
A0(DDR200@CL=2)
1200
1880
600
800
144
128
200
320
960
920
24
24
12
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.0 Dec. 2001
Optional
Notes