m470t2953bs0-cd5cc Samsung Semiconductor, Inc., m470t2953bs0-cd5cc Datasheet
m470t2953bs0-cd5cc
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m470t2953bs0-cd5cc Summary of contents
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Unbuffered SODIMMs DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb B-die INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED ...
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... Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16 • All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. Address Configuration Organization 64Mx8(512Mb) based Module 32Mx16(512Mb) based Module Density Organization Component Composition 256MB 32Mx64 ...
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... DQS2 Note : Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules. Pin Description Pin Name CK0,CK1 Clock Inputs, positive line CK0,CK1 Clock Inputs, negative line CKE0,CKE1 Clock Enables RAS Row Address Strobe ...
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... DDR2 SDRAMs and is sent at the leading edge of the data In/Out DQS0~DQS7 window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS If the module operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately ...
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... DQ25 I/O 9 DQ26 I/O 10 DQ27 I/O 11 DQ28 I/O 12 DQ29 I/O 13 DQ30 I/O 14 DQ31 I/O 15 3Ω BA0 - BA1 A0 - A13 RAS CAS WE V SPD DD V REF 512MB, 64Mx64 Module M470T6554BG(Z)3/M470T6554BG(Z)0 DQS4 LDQS LDQS K D DQS4 E T LDM E T DM4 I I I/O 2 I/O 3 I/O 4 ...
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... DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 3Ω BA0 - BA1 A0 - A13 RAS CAS WE V SPD DD V REF 256MB, 32Mx64 Module M470T3354BG(Z)3/M470T3354BG(Z)0 DQS4 LDQS LDQS D K DQS4 LDM T E DM4 DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 ...
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... RAS DDR2 SDRAMs D0 - D15 CAS DDR2 SDRAMs D0 - D15 WE DDR2 SDRAMs D0 - D15 V SPD Serial DDR2 SDRAMs D0 - D15 REF V DDR2 SDRAMs D0 - D15 DDR2 SDRAMs D0 - D15, SPD SS 1GB, 128Mx64 Module M470T2953BS(Y)3/M470T2953BS(Y)0 1 DQS4 CS0 DQS DQS D K DQS4 ...
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Unbuffered SODIMMs Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL ...
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Unbuffered SODIMMs Operating Temperature Condition Symbol TOPER Operating Temperature Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...
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Unbuffered SODIMMs IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t ...
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... IDD3P-F 120 IDD3P-S IDD3N 280 IDD4W 920 IDD4R 820 IDD5B 780 IDD6 IDD7 1,560 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap VDD= 1.9V) A LD5 (DDR533@CL=4) (DDR400@CL=3) 460 560 64 64 200 200 ...
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... IDD4R 2,000 IDD5B 2,120 IDD6 IDD7 2,760 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Input/Output Capacitance (V Parameter Non-ECC Input capacitance, CK and CK Input capacitance, CKE , CS, Addr, RAS, CAS, WE Input/output capacitance, DQ, DM, DQS, DQS * DM is internally loaded to match DQ and DQS identically ...
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Unbuffered SODIMMs Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM (0 °C < T < 95 °C; V CASE DDQ Refresh Parameters by Device Density Parameter Refresh to active/Refresh command time Average periodic refresh interval Speed Bins ...
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Unbuffered SODIMMs Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level ...
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Unbuffered SODIMMs Parameter CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power ...
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... Unbuffered SODIMMs Physical Dimensions 11.40 16. FRONT SIDE 4.20 2.70 ± 0.10 1.50 ± 0.10 1.0 ± 0.05 4.00 ± 0.10 The used device is 32M x16 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51163QB 32Mbx16 based 64Mx64 Module(2 Rank) M470T6554BG(Z)3/M470T6554BG(Z)0 67.60 mm 2.00 b 199 47.40 63.00 200 67.60 mm DETAIL a BACK SIDE 4.00 ± 0.10 1.0 ± 0.05 1.80 ± 0.10 2.40 ± 0.10 4 ...
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... Unbuffered SODIMMs Physical Dimensions 11.40 16. FRONT SIDE 4.20 2.70 ± 0.10 1.50 ± 0.10 1.0 ± 0.05 4.00 ± 0.10 The used device is 32M x16 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51163QB 32Mbx16 based 32Mx64 Module(1 Rank) M470T3354BG(Z)3/M470T3354BG(Z)0 67.60 mm 2.00 b 199 47.40 63.00 200 67.60 mm DETAIL a BACK SIDE 4.00 ± 0.10 1.0 ± 0.05 1.80 ± 0.10 2.40 ± 0.10 4 ...
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... Unbuffered SODIMMs Physical Dimensions 11.40 16. FRONT SIDE 4.20 2.70 ± 0.10 1.50 ± 0.10 1.0 ± 0.05 4.00 ± 0.10 The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QB 64Mbx8 based 128Mx64 Module(2 Ranks) M470T2953BS(Y)3/M470T2953BS(Y)0 67.60 mm 2.00 SPD b 199 47.40 63.00 200 67.60 mm DETAIL a BACK SIDE 4.00 ± 0.10 1.0 ± 0.05 1.80 ± 0.10 2.40 ± ...
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Unbuffered SODIMMs Revision History Revision 1.0 (Jan. 2004) - Initial Release Revision 1.1 (Jun. 2004) - Added lead-free part number in the ordering information - Changed IDD2P Revision 1.2 (Jul. 2004) - Added current values and part ...