m470t2953bs0-cd5cc Samsung Semiconductor, Inc., m470t2953bs0-cd5cc Datasheet - Page 2

• Manufacturer Part Number: m470t2953bs0-cd5cc
• Description: 200pin Unbuffered Sodimm Based 512mb B-die 64bit Non-ecc
• Manufacturer: Samsung Semiconductor, Inc.

DDR2 Unbuffered SODIMM Ordering Information
Note: “Z” and “Y” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Features
Address Configuration
256MB, 512MB, 1GB Unbuffered SODIMMs
M470T3354BG(Z)3-CD5/CC
M470T3354BG(Z)0-CD5/CC
M470T3354BZ3-LD5/CC
M470T3354BZ0-LD5/CC
M470T6554BG(Z)3-CD5/CC
M470T6554BG(Z)0-CD5/CC
M470T6554BZ3-LD5/CC
M470T6554BZ0-LD5/CC
M470T2953BS(Y)3-CD5/CC
M470T2953BS(Y)0-CD5/CC
M470T2953BY3-LD5/CC
M470T2953BY0-LD5/CC
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
• V
• 200 MHz f
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than a T
• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS
-
DDQ
support High Temperature Self-Refresh rate enable feature
32Mx16(512Mb) based Module
64Mx8(512Mb) based Module
CL-tRCD-tRP
Speed@CL3
Speed@CL4
= 1.8V ± 0.1V
Part Number
Organization
CK
for 400Mb/sec/pin, 267MHz f
D5(DDR2-533)
4-4-4
400
533
Density
256MB
256MB
256MB
256MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
Row Address
CK
A0-A13
A0-A12
for 533Mb/sec/pin
CASE
CC(DDR2-400)
Organization
128Mx64
128Mx64
128Mx64
128Mx64
3-3-3
32Mx64
32Mx64
32Mx64
32Mx64
64Mx64
64Mx64
64Mx64
64Mx64
85°C, 3.9us at 85°C < T
400
400
Column Address
A0-A9
A0-A9
Mbps
Mbps
Unit
CK
Component Composition
32Mx16(K4T51163QB)*4
32Mx16(K4T51163QB)*4
32Mx16(K4T51163QB)*4
32Mx16(K4T51163QB)*4
32Mx16(K4T51163QB)*8
32Mx16(K4T51163QB)*8
32Mx16(K4T51163QB)*8
32Mx16(K4T51163QB)*8
64Mx8(K4T51083QB)*16
64Mx8(K4T51083QB)*16
64Mx8(K4T51083QB)*16
64Mx8(K4T51083QB)*16
CASE
< 95 °C
Bank Address
BA0-BA1
BA0-BA1
Rev. 1.5 Aug. 2005
DDR2 SDRAM
Number of
Rank
Auto Precharge
1
1
1
1
2
2
2
2
2
2
2
2
A10
A10
Height
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm