hys64t128020edl Qimonda, hys64t128020edl Datasheet - Page 20
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hys64t128020edl
Manufacturer Part Number
hys64t128020edl
Description
200-pin Small-outlined Ddr2 Sdram Modules
Manufacturer
Qimonda
Datasheet
1.HYS64T128020EDL.pdf
(43 pages)
Rev. 1.12, 2007-10
10312006-I253-V1V0
Parameter
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
Minimum time clocks remain ON after
CKE asynchronously drops LOW
DQ and DM input hold time (differential
data strobe)
DQ and DM input hold time (single ended
data strobe)
DQ and DM input pulse width (each
input)
DQS input HIGH pulse width (write cycle)
DQS input LOW pulse width (write cycle)
DQS-DQ skew (for DQS & associated
DQ signals)
Write command to 1st DQS latching
transition
DQ and DM input setup time (differential
data strobe)
DQ and DM input setup time (single
ended data strobe)
DQS falling edge hold time from CK
(write cycle)
DQS falling edge to CK setup time (write
cycle)
Four Activate Window period
Clock half period
Data-out high-impedance time from CK /
CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CCD
CH
CKE
CL
DAL
DELAY
DH.BASE
DH1.BASE
DIPW
DQSH
DQSL
DQSQ
DQSS
DS.BASE
DS1.BASE
DSH
DSS
FAW
HP
HZ
IH.BASE
IPW
IS.BASE
LZ(DQ)
LZ(DQS)
MOD
MRD
DRAM Component Timing Parameter by Speed Grade - DDR2–533
DDR2–533
2
0.45
3
0.45
WR +
t
225
–25
0.35
0.35
0.35
—
– 0.25
100
–25
0.2
0.2
50
MIN. (
—
375
0.6
250
2 ×
t
0
2
Min.
IS
AC.MIN
20
+
t
t
AC.MIN
CK
t
t
CL,
RP
+
t
t
IH
CH
)
Max.
—
—
—
––
––
—
—
—
—
300
+ 0.25
—
—
—
—
—
t
—
—
—
t
t
12
—
0.55
0.55
AC.MAX
AC.MAX
AC.MAX
Small Outlined DDR2 SDRAM Modules
HYS64T128020EDL–[2.5/3S/3.7]–B
Unit
t
t
t
t
t
ns
ps
ps
t
t
t
ps
t
ps
ps
t
t
ns
ps
ps
t
ps
ps
ps
ns
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Internet Data Sheet
TABLE 15
Notes
7)
8)
9)
10)
11)
11)
11)
11)
13)
12)
13)
11)
11)
14)
14)
2)3)4)5)6)