hys64t128000eu-3s-c2 Qimonda, hys64t128000eu-3s-c2 Datasheet - Page 23

• Manufacturer Part Number: hys64t128000eu-3s-c2
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Qimonda

3.3.3
This chapter describes the ODT AC electrical characteristics.
1) New units, “t
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 0.51, 2007-12
12032007-I9KE-FFWO
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
under operation. Unit “
DDR2-533, “
be registered at
the ODT resistance is fully on. Both are measured from
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
Both are measured from
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
CK.AVG
t
CK
” is used for both concepts. Example:
T
m
” and “
+ 2, even if (
ODT AC Electrical Characteristics
n
CK
n
t
AOFD
” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
CK
”, are introduced in DDR2-667 and DDR2-800. Unit “
, which is interpreted differently per speed bin. For DDR2-667/800, if
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
T
m
+ 2 -
T
m
) is 2 x
t
CK.AVG
t
XP
t
= 2 [
AOND
+
t
n
ERR.2PER(Min)
, which is interpreted differently per speed bin. For DDR2-667/800,
CK
Values
Min.
2
t
t
2.5
t
t
3
8
] means; if Power Down exit is registered at
AC.MIN
AC.MIN
AC.MIN
AC.MIN
23
+ 2 ns
+ 2 ns
.
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3/3S]–C2
t
CK.AVG
Max.
2
t
2
2.5
t
2.5
—
—
AC.MAX
AC.MAX
t
CK +
t
” represents the actual
CK +
t
+ 0.7 ns
AC.MAX
+ 0.6 ns
Unbuffered DDR2 SDRAM Modules
t
AC.MAX
+ 1 ns
t
CK(avg)
Advance Internet Data Sheet
+ 1 ns
= 3 ns is assumed,
T
m
, an Active command may
t
CK.AVG
Unit
n
ns
ns
n
ns
ns
n
n
CK
CK
CK
CK
TABLE 15
of the input clock
Note
1)
1)2)
1)
1)
1)3)
1)
1)
1)
t
AOFD
t
AOND
is 1.5
is