hys64t256022edl Qimonda, hys64t256022edl Datasheet - Page 4

• Manufacturer Part Number: hys64t256022edl
• Description: 200-pin Dual Small-outline-ddr2-sdram Modules
• Manufacturer: Qimonda

1.2
The
module family are Small Outline modules “SO-DIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 256M × 64 (2 GB)
organization and density, intended for mounting into 200-pin
connector sockets.
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T256022EDL–3.7–B, indicating
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200S–444–12–D0”, where
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2006-11
11172006-DXYK-2PPW
Product Type
PC2–6400
HYS64T256022EDL–25F–B
PC2–6400
HYS64T256022EDL–2.5–B
PC2–5300
HYS64T256022EDL–3–B
PC2–5300
HYS64T256022EDL–3S–B
PC2–4200
HYS64T256022EDL–3.7–B
DIMM Density
2 GByte
Product Type
HYS64T256022EDL
Rev. “B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
this data sheet.
4200S means SO-DIMM modules with 4.26 GB/sec Module Bandwidth and “444–12” means Column Address Strobe (CAS) latency = 4,
Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on
the Raw Card “D”.
Qimonda
1)
1)
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Module
Organization
256M ×64
Description
DRAM Components
HYB18T2G802BF
Compliance Code
2GB 2R×8 PC2–6400S–555–12–D0
2GB 2R×8 PC2–6400S–666–12–D0
2GB 2R×8 PC2–5300S–444–12–D0
2GB 2R×8 PC2–5300S–555–12–D0
2GB 2R×8 PC2–4200S–444–12–D0
Memory
Ranks
2
ECC/
Non-ECC
Non-ECC
1)
2)
4
DRAM Density
2 ×1 Gbit
Ordering Information for RoHS Compliant Products
The memory array is designed with stacked 1 Gbit Double-
Data-Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB. The DIMMs feature
serial presence detect based on a serial E
using the 2-pin I
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
# of
SDRAMs
16
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
# of row/bank/columns bits
14/3/10
Small Outline DDR2 SDRAM Modules
2
C protocol. The first 128 bytes are
DRAM Organisation
2× 128M ×8
Components on Modules
1 Gbit (×8)
1 Gbit (×8)
1 Gbit (×8)
1 Gbit (×8)
1 Gbit (×8)
SDRAM Technology
Internet Data Sheet
Address Format
TABLE 2
TABLE 3
TABLE 4
2
PROM device
Raw Card
D
Chapter 6
Note
2)
of