saa5288 NXP Semiconductors, saa5288 Datasheet - Page 27

• Manufacturer Part Number: saa5288
• Description: Microcontroller With Full Screen Screen Display
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.10
Setting the TXT7.DOUBLE HEIGHT bit causes the normal
height of all display characters to be doubled and the
whole of the display area to be occupied by half of the
display rows. Characters normally displayed double height
will be displayed quadruple height when this bit is set.
Rows 12 to 24 can be enlarged, rather than rows 0 to 11,
by setting the TXT7.TOP/BOTTOM bit.
This feature can be used for either a user controlled
‘enlarge’ facility or to provide very large characters for the
OSD.
The display of rows 0 to 23 can be disabled by setting the
TXT0.DISPLAY STATUS ROW ONLY bit.
The Fastext prompt row (packet 24) can be displayed from
the extension packet memory by setting the
TXT0.DISPLAY X/24 bit. When this bit is set the data
displayed on display row 24 is taken from row 0 in the
extension packet memory.
When the display from extension packet block option is
enabled, the display will revert to row 24 of the basic page
memory if bit 3 of the link control byte in packet 27 is set.
7.11
The display synchronises to the device’s HSync and
VSync inputs. A typical configuration is shown in Fig.7.
1997 Jun 24
TV microcontroller with full screen
On Screen Display (OSD)
Other display features
Display timing
handbook, halfpage
TUNER/IF
CVBS
Fig.7 Timing configuration.
DECODING
CIRCUITS
VIDEO
SYNC
27
SAA5288
HSYNC, VSYNC
RGB
The HSync and VSync signals are derived from the signals
driving the deflection coils of the TV. Locking the display to
the signals from the scan circuits allows the device to give
a stable display under almost all signal conditions.
The polarity of the input signals which the device is
expecting can be set using the TXT1.H polarity and
TXT1.V polarity bits. If the polarity bit is a logic 0, a positive
going signal is expected and if it is a logic 1, a negative
going signal is expected.
7.12
Every time an HSync pulse is received the display
resynchronizes to its leading edge. To get maximum
display stability, the HSync input must have fast edges,
free of noise to ensure that there is no uncertainty in the
timing of the signal to which the display synchronisation
circuits must lock.
The display area starts 17.2 s into the line and lasts for
40 s. The display area will be in the centre of the screen
if the HSync pulse is aligned with line flyback signal.
Therefore, it is better to derive HSync directly from the line
flyback or from an output of the line output transformer
than from, say, slicing the sandcastle signal as this would
introduce delays which would shift the display to the right.
Horizontal timing
RGB, VDS
FRAME
DISPLAY
CRT
MGL120
Preliminary specification
SAA5288