saa5288 NXP Semiconductors, saa5288 Datasheet - Page 8

• Manufacturer Part Number: saa5288
• Description: Microcontroller With Full Screen Screen Display
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7
7.1
The functionality of the microcontroller used with this
family is described with reference to the industry-standard
80C51 microcontroller. A full description of its functionality
can be found in “80C51-Based; 8-bit Microcontrollers,
Data Handbook IC20” . Using the 80C51 as a reference,
the changes made to this family fall into two categories:
7.2
7.2.1
The IP SFR is not implemented and all interrupts are
treated with the same priority level. The normal priority of
interrupts is maintained within the level.
Table 2 Interrupts and vector address
7.2.2
The SAA5288 does not support the use of off-chip
program memory or off-chip data memory.
7.2.3
Idle and Power-down modes are not supported.
Consequently, the respective bits in PCON are not
available.
7.2.4
The 80C51 UART is not available. As a consequence the
SCON and SBUF SFRs are removed and the ES bit in the
IE SFR is unavailable.
1997 Jun 24
Reset
External INT0
Timer 0
External INT1
Timer 1
Byte I
Bit I
Features not supported by the SAA5288
Features found on the SAA5288 but not supported by
the 80C51.
TV microcontroller with full screen
On Screen Display (OSD)
INTERRUPT SOURCE
FUNCTIONAL DESCRIPTION
2
C-bus
2
Microcontroller
80C51 features not supported
C-bus
I
O
I
UART
NTERRUPT PRIORITY
DLE AND
FF
-
CHIP MEMORY
FUNCTION
P
OWER
-
DOWN MODES
VECTOR ADDRESS
(HEX)
00B
01B
02B
000
003
013
053
8
7.3
The following features are provided in addition to the
standard 80C51 features.
7.3.1
The external INT1 interrupt is modified to generate an
interrupt on both the rising and falling edges of the INT1
pin, when EX1 bit is set. This facility allows for software
pulse-width measurement for handling of a remote control.
7.3.2
For reasons of compatibility with the SAA5290, SAA5291,
SAA5291A and SAA5491 all contain a bit level serial I/O
which supports the I
the serial I/O pins. These two pins meet the I
specification concerning the input levels and output drive
capability see “The I
specifications)” . Consequently, these two pins have an
open-drain output configuration. All the four following
modes of the I
Three SFRs support the function of the bit-level I
hardware: S1INT, S1BIT and S1SCS and are enabled by
setting register bit TXT8.I
7.3.3
The byte level serial I/O supports the I
P1.6/SCL and P1.7/SDA are the serial I/O pins. These two
pins meet the I
levels and output drive capability. Consequently, these two
pins have an open-drain output configuration.
The byte level I
serial port on the 8xC552. The operation of the subsystem
is described in detail in the 8xC552 data sheet described
in “80C51-Based; 8-bit Microcontrollers Data Handbook
IC20” .
Four SFRs support the byte level I
S1CON, S1STA, S1DAT and S1ADR. They are enabled
by setting register bit TXT8. I
7.3.4
Port pins P0.5 and P0.6 have a 10 mA current sinking
capability to enable LEDs to be driven directly.
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
Additional features
B
I
B
LED
NTERRUPTS
IT
YTE
L
EVEL
SUPPORT
2
L
2
2
C-bus are supported.
C-bus specification concerning the input
EVEL
C-bus serial port is identical to the I
I
2
2
2
C-
C-bus. P1.6/SCL and P1.7/SDA are
C-bus and how to use it (including
I
2
C-
BUS
BUS
2
C SELECT to logic 0.
I
NTERFACE
2
I
C SELECT to logic 1.
NTERFACE
Preliminary specification
2
C-bus hardware:
2
C-bus protocol.
SAA5288
2
C-bus
2
C-bus
2
C-bus