saa5233 NXP Semiconductors, saa5233 Datasheet - Page 10

• Manufacturer Part Number: saa5233
• Description: Dual Standard Decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Control of device
The function of the device is controlled via the I
Pin AD provides a choice of two alternative addresses.
The PDC acquisition section requires little software control
apart from enabling the interrupts which occur when data
is found. Interrupts can be enabled for either Teletext
packet 8/30/2 or VPS and both can be enabled to allow for
the presence of both standards being transmitted on the
same TV channel. The interrupt register is accessed as
address 01 WRITE, see Section “Register 01: Interrupt
(reset state X00X XXXX)”.
When an interrupt is signalled, a bit is set in the status
register to indicate its source. Information about the
received PDC data is given in the status register D5 and
D6. The microcontroller must service the ‘data received’
interrupts within 40 ms (VPS) or 200 ms
(Teletext packet 8/30/2), since new data may be written
after this period. The status register is accessed as
address 00 READ; see Section
“Register 00:Control/Status (reset state XXX0 XX00)”.
When the status register has been read the data received
flags and interrupt signal are reset.
Data of both types is constantly received and stored, but
can be selectively acquired by setting bits D1 and D0 of the
control register. This allows acquisition of only Teletext
packet 8/30/2 on every VBI line or only VPS data on every
VBI line. The control register is accessed as address
00 WRITE, see Section “Register 00:Control/Status (reset
state XXX0 XX00)”.
Storage of PDC data
The PDC data memory is accessed at address 02 (HEX)
to 31 (HEX). The exact addresses of Teletext packet
8/30/2 and VPS data is shown in Table 5.
T
The Teletext packet 8/30/2 data is stored after hardware
Hamming correction. There are 4 data bits stored in the
lower nibble of each byte in address 11 (HEX)
to 1D (HEX); see Table 13, in the order shown in Table 5.
The status message, which is odd parity coded, is stored
as a byte which represents a Teletext character in address
1E (HEX) to 31 (HEX); see Table 14.
VPS
The VPS data from Line 16 is stored in register address
02 (HEX) to 0F (HEX) in the order shown in Table 5. VPS
June 1994
ELETEXT DATA
Dual standard PDC decoder
DATA
2
C-bus.
10
data is biphase decoded and stored with 4 data bits stored
in the lower nibble of each byte, in the same way as
Teletext packet 8/30/2 data; see Tables 11 and 12. In
addition to the VCR data, Word 4
(Program Source Identification, ASCII sequential) is
stored, which may be useful for future applications.
The stored data is read via the I
Multiple reception/majority error correction of the data is
the responsibility of the control software, the device simply
stores the data as transmitted after Hamming or biphase
decoding. As both VPS and Teletext packet 8/30/2 signals
are stored separately, it is possible to deal with future
situations where both EBU PDC System A and EBU PDC
System B transmissions may be present on the same TV
channel, the defaults and level of service being chosen by
the software control.
Error indication
Indication of errors in the received data is given in two
ways and is programmable by setting bit D4 in the control
register.
The first is a flag to indicate Hamming or biphase errors
and is stored with the related data in bit 0 of the upper
nibble of the data byte.
The second is no interrupt which is sent to the
microcontroller but the data signal quality bit (D7) is set.
The level of interrupt is controlled by the Interrupt
Error Level bit which is D4 of the control register. If this bit
is not set then an interrupt only occurs if an error free line
of either Teletext packet 8/30/2 or VPS data is received
and stored in RAM. If this bit is set then an interrupt occurs
if the correct framing code and Teletext packet header
8/30/2 is found, or the correct start code for VPS data is
found. The data is then stored in the RAM with any errors
indicated in the upper nibble. This may be used by more
sophisticated software, which could decide the importance
of an error in a particular nibble.
I
F
2
EATURES
C-bus interface
Standard I
Operates from 0 to 100 kHz
Acknowledge function is performed
Auto-increment between registers and direct addressing
Selectable I
address pin AD.
2
C-bus slave transceiver
2
C-bus slave address dependent on
2
C-bus in the normal way.
Objective specification
SAA5233