saa5233 NXP Semiconductors, saa5233 Datasheet - Page 14

• Manufacturer Part Number: saa5233
• Description: Dual Standard Decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Register 1E to 31D (HEX): Status display message
Data is stored as bytes which represent a Teletext character. The data is odd parity checked, if a parity error occurs this
causes the byte not to be written to the RAM. The MSB is not used and is fixed to logic 0.
Table 14 Register 11.
I
The slave address for the device can take one of two
values dependent on the state of the input pin AD.
Table 15 Device address.
Note
1. Where X is the R/W bit.
I
The I
in Table 16
June 1994
2
2
C-bus slave address
C-bus increment
Dual standard PDC decoder
2
D7
C-bus will also increment between registers as listed
AD
0
1
DATA BIT 6
D6
SLAVE ADDRESS
DATA BIT 5
0010 001X
0010 000X
D5
(1)
(1)
DATA BIT 4
D4
14
DATA BIT 3
Table 16 Increment between registers.
Addressing any register in either of these ranges will
initialize an increment until the final stop value provided
each byte is acknowledged by the receiver.
Initialization during power-up
The device has an internal power-on reset unit which is
used to reset the I
transceiver. It also initializes the device to receive only
completely valid Teletext packet 8/30/2 and VPS data. The
interrupt signals for both Teletext packet 8/30/2 and VPS
are disabled.
02 to 0F (HEX) VPS data bytes
11 to 31 (HEX) Teletext packet 8/30/2 data bytes and
ADDRESS
D3
DATA BIT 2
Status display message
2
D2
C-bus interface to be a slave
DATA BIT 1
CONTENTS
D1
Objective specification
SAA5233
DATA BIT 0
D0