w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 114

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
WINBOND ELECTRONICS CORP. AMERICA
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
MWIEN. When this bit is 1b, Memory write and invalidate commands are enabled, when acting
as a bus master. When this bit is 0b, only memory writes can be used. This bit is a 0b after a
reset.
This bit is not used and is hardwired to a logic 0.
BMEN. This bit must be set to allow the W83C554F to perform bus master cycles. Writing a 1b
to this bit will set it. Also, writing a 1b to bit 0 (Start/Stop Bus Master) of the Primary or
Secondary Bus Master IDE Command Register will set this bit. This bit is a 0b after a reset.
This bit is not used and is hardwired to a logic 0b.
IOEN. When bit 0 is set to a 1b, IDE I/O address decodes, based on the W83C554F's
configuration, are enabled. Primary and/or secondary port I/O addresses are decoded if they
are also enabled in the IDE Control/Status Register. They will be the default address range,
unless the Base Address Registers are enabled and programmed. In this case, the Base
Address Registers determine the addresses to be decoded.
Register Information
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