hdmp-1526 ETC-unknow, hdmp-1526 Datasheet - Page 13

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hdmp-1526

Manufacturer Part Number
hdmp-1526
Description
Fibre Channel Transceiver Chip
Manufacturer
ETC-unknow
Datasheet
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
Bypass capacitors should be
liberally used and placed as close
as possible to the appropriate
power supply pins of the HDMP-
1526 as shown on the schematic
of Figure 11. All bypass chip
capacitors are 0.1 F. The
VCC_RXA and VCC_TXA pins are
the analog power supply pins for
the PLL sections. The voltage into
these pins should be clean with
minimum noise. The PLL loop
filter capacitors and their pin
locations are also shown on
Figure 11. Notice that only two
capacitors are required: C
the transmitter and C
receiver. Nominal capacitance is
0.01 F. The voltage across the
capacitors is on the order of 1
volt, so the capacitor can be a
low voltage type and physically
small. The PLL capacitors are
placed physically close to the
appropriate pins on the HDMP-
1526. Keeping the lines short will
prevent them from picking up
stray noise from surrounding
lines or components.
Transceiver Package
Information
The HDMP-1526 is constructed
of a single integrated circuit
packaged in a 14x14 mm
EDQuad package. This package
was designed to provide
enhanced power dissipation, thus
allowing for smaller package
dimensions. The package
conforms to the industry standard
JEDEC land pattern for 14x14
mm devices. As shown in Figure
12, the die is attached to a
copper heatsink using thermally
conductive epoxy. This allows for
694
PLLR
for the
PLLT
for
the power dissipated by the IC to
be directly connected to the
ambient environment, thereby
minimizing the jc of the device.
Figure 12. Power Supply Bypass.
Figure 13. Package Cross Section of HDMP-1526.
COPPER HEATSINK
V
V
CC
CC
GND_TXTTL
TXCAP0
C
PLLT
* SUPPLY VOLTAGE INTO V
BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS
ARE 0.1 µF. THE PLL FILTER CAPACITORS ARE 0.01 µF.
WIRE BOND
V
V
CC
CC
GND_TXTTL
GND_TXA
_TXTTL
_TXTTL
V
V
CC
CC
V
CC
*
V
CC
NICKEL PLATING
TOP VIEW
DIE
V
CC
CC
_RXA AND V
V
CC
V
CC
CC
V
V
V
CC
CC
CC
_TXA SHOULD
V
CC
_RXTTL
_RXTTL
*
CERAMIC
C
RXCAP0
GND_RXTTL
PLLR
LEAD
GND_RXTTL
V
V
CC
CC

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