pth12040 Astec Powe, pth12040 Datasheet - Page 12

• Manufacturer Part Number: pth12040
• Description: Pth12040 12vin Single
• Manufacturer: Astec Powe

8. Thermal Information
8.1 Thermal Reference Points
The electrical operating conditions namely:
• Input voltage, V
• Output voltage, V
• Output current, I
determine how much power is dissipated within the converter. The
following parameters further influence the thermal stresses
experienced by the converter:
• Ambient temperature
• Air velocity
• Thermal efficiency of the end system application
• Parts mounted on system PCB that may block airflow
• Real airflow characteristics at the converter location
8.2 Safe Operating Area Curve
Thermal characterization data is presented in the datasheet in a safe
operating area curve format which is repeated here in Figure 12.
This SOA curve shows the load current versus the ambient air
temperature and velocity.
8.3 Thermal Test Set-up
All of the data was taken with the converter soldered to a test board
which closely represents a typical application. The test board is a
1.6mm, eight layer FR4 PCB with the inner layers consisting of 2oz
power and ground planes. The top and bottom layers contain a
minimal amount of metalization. A board to board spacing of 1 inch
was used. The data represented by the 0m/s curve indicate a
natural convection condition i.e. no forced air. However, since the
thermal performance is heavily dependent upon the final system
application, the user needs to ensure the thermal reference point
temperatures are kept within the recommended temperature rating.
It is recommended that the thermal reference point temperatures are
measured using either AWG #36 or #40 gauge thermocouples or an
IR camera. In order to comply with stringent Artesyn derating
criteria, the ambient temperature should never exceed 85°C. Please
contact Artesyn Technologies for further support.
1 1 2 2
90
80
70
60
50
40
30
20
0
Figure 12 - Safe Operating Curve
10
in
OUTPUT CURRENT (A)
o
o
PTH12040W V out = 3.3V
20
File Name: an_pth12040.pdf Rev (02): 21 Dec 2005
30
40
50
Nat conv
100 LFM
200 LFM
400 LFM
9. Use in a Manufacturing Environment
9.1 Recommended Land Pattern
It is recommended that the customer uses a solder mask defined
land pattern similar to that shown in Figures 13 and 14.
Power pin connection should utilize four or more vias to the interior
power plane of 0.025 (0.63) I.D. per input, ground and output pin (or
the electrical equivalent. All power pins need to be connected.
As a surface-mount power component, interconnection to internal
power planes will typically be required. This is accomplished by
placing a number of vias between the SMT pad and the relevant
plane. the number and exact location of these vias should be
determined based on electrical resistivity, current flow and thermal
requirements.
Figure 13 - Recommended Land Pattern (Through - Hole Model)
Figure 14 - Recommended Land Pattern (Surface Mount Model)
(23.49)
(23.49)
0.925
0.925
0.080 (2.03)
(1.52)
0.125 (3.17)
6 Places
0.080 (2.03)
(1.52)
0.060
0.125 (3.17)
6 Places
0.060
(3.17)
3 Places
0.125
(3.17)
3 Places
0.125
17
17
18
19
20
PTH12040 Single Series | Application Note 193
1
16
20
18
19
(9.52)
0.375
(9.52)
1
0.375
16
(9.52)
(9.52)
0.375
0.375
15
2
2 Places
(6.35)
0.250
14
15
2
2 Places
(6.35)
1.875 (47.62)
0.250
2.085 (52.96)
13
3
14
(9.52)
0.375
(9.52)
0.375
1.875 (47.62)
2.085 (52.96)
13
3
TOP VIEW
(9.52)
(9.52)
0.375
0.375
12
4
11
12
10
4
5
(9.52)
(9.52)
0.375
11
0.375
10
5
6
9
(9.52)
(9.52)
0.375
0.375
7
8
0.125 (3.17)
6
9
(27.56)
1.085
7
8
ø
Plated through hole.
0.055 (1,40) Min. 20 Places
0.125 (3.17)
ø
Paste screen opening:
0.080 (2.03) to 0.085 (2.16)
Paste screen thickness:
0.006 (0.150)
(27.56)
0.085 (2.16) 20 Places
1.085