ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 20

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 6. Basic Logic Blocks, Receive Path, Single Channel (Typical Reference Clock Frequency)
Each channel provides its own received clock, received data and K-character detect signals to the FPGA logic.
Incoming data from multiple channels can be aligned using comma (/K/) characters or /A/ character (as specified
either in Fibre Channel specifications or in IEEE 802.3ae for XAUI based interfaces). If the 8b/10b decoders are
bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in this
8b/10b bypass mode.
Detailed descriptions of data synchronization, of the SERDES, DEMUX and Multi-Channel Alignment blocks and of
the Fibre Channel and XAUI state machines are given in following sections. Receive clock distribution is described
in a later section of this data sheet.
Synchronization
The SERDES RX logic performs four levels of synchronization on the incoming serial data stream. Each level
builds upon the previous, providing first bit, then byte (character), then channel (32-bit word), and finally multi-chan-
nel alignment. Each step is described functionally in the following paragraphs. The details of the logical implemen-
tations are described in subsequent sections.
Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transi-
tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. If the PLL
is unable to lock to the serial data stream, it instead locks to REFCLK[A:B] to stabilize the voltage-controlled oscil-
lator (VCO), and periodically switches back to the serial data stream to again attempt synchronization. This pro-
cess continues until a valid input data stream is detected and lock is achieved. The CDR can maintain lock on data
as long as the input data stream contains an adequate data “eye” (i.e., jitter is within specification) and the maxi-
mum data stream run length is not exceeded.
RSYS_CLK_x#
MRWDxx[39:0]
CV_SELxx
RCK78[A:B]
FPGA
FPGA
Logic
Logic
78.125 MHz
78.125 MHz
78.125 MHz
78.125 MHz
RWCKxx
4 bits k-ctrl
32-bit data
Alignment
Channel
40
Alignment Block
Multi-
MUX
FIFO
Multi-Channel
36
(x40)
Synchronization
MUX
2:1
Align Character Detect
See Table 8
RCKSEL[0:1][A:B]
Status bits
RWDxx[31:0]
RALIGNxx[3:0]
RWBIT8xx[3:0]
78.125 MHz Clock
3
32-bit data
4 bits k-control
RWBIT9xx[3:0]
{
From other channel
or channels
32
Logic Common to Block
4
4
4
From Control
DEMUX
Machine
(x 10)
Register
XAUI
State
1:4
SWDSYNC_xx
Fibre Channel State
SRBD_xx[0:9]
312.5 MHz
Clocks
SCVxx
10
DEMUX
20
SBYTSYNC_xx
Machine
Block
To other
channel or
channels
ORCA ORT42G5 and ORT82G5 Data Sheet
2
Encoder
bypass)
8B/10B
(with
PLL
{
Align
Byte
RX SERDES Block
DEMUX
REFCLK
1:10
CDR
Buffer
For ORT42G5:
xx = [AC, AD, BC, BD]
x# = [A2, B2]
For ORT82G5:
xx = [AA, AB, ... BD]
x# = [A1, ...B2]
Buffer
CML
REFCLKP_[A:B]
REFCLKN_[A:B]
HDINP_xx
HDIN_xx
Backplane
156.25 MHz
Serial
Link