ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 62

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), xx = [AC, AD, BC or BD]
30024 - AC
30034 - AD
30124 - BC
30134 - BD
SERDES Global Control Registers (Read Write) - Act on Both Channels in SERDES Block A or SERDES Block B.
30005 - A
30105 - B
30006 - A
30106 - B
Absolute
Address
(0x)
[3:6] Not used
[0:4] TestMode[A:B]
[6:7] Reserved
Bit
[0]
[1]
[2]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[5]
Reserved
MASK_xx
SWRST_xx
TESTEN_xx
Reserved
GMASK_[A:B]
GSWRST_[A:B]
GPWRDNT_[A:B]
GPWRDNR_[A:B]
Reserved
Not used
GTESTEN_[A:B]
Not used
Name
Reset
Value
Desc.
Desc.
(0x)
See
See
Bit
Bit
00
Reserved, must be 0. Set to 0 on device reset.
Transmit and Receive Alarm Mask Bit, Channel xx. When MASK_xx = 1,
the transmit and receive alarms of a channel are prevented from gener-
ating an interrupt (i.e., they are masked or disabled). The MASK_xx bit
overrides the individual alarm mask bits in the Alarm Mask Registers.
MASK_xx = 1 on device reset.
Transmit and Receive Software Reset Bit, Channel xx. When
SWRST_ss = 1, this bit provides the same function as the hardware
reset, except that all configuration register settings are unaltered. This is
not a self-clearing bit. Once set, this bit must be manually set and
cleared. SWRST = 0 on device reset.
Not used
Transmit and Receive Test Enable Bit, Channel xx. When TESTEN_xx =
1, the transmit and receive sections are placed in test mode. The
TestMode_[A:B][4:0] bits in the Global Control Registers specify the par-
ticular test, and must also be set.
Note: When the global test enable bit GTESTEN_[A:B] = 0, the individual
channel test enable bits are used to selectively place a channel in test or
normal mode. When GTESTEN_[A:B] = 1, all channels in a block are set
to test mode regardless of their TESTEN setting. TESTEN_xx = 0 on
device reset.
Reserved, must be 0. Set to 0 on device reset.
Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms
of both channels in the SERDES block are prevented from generating an
interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit over-
rides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset.
Software reset bit. The GSWRST_[A:B] bit provides the same function
as the hardware reset for the transmit and receive sections of both chan-
nels, except that the device configuration settings are not affected when
GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once set, this
bit must be manually set and cleared. The GSWRST_[A:B] bit overrides
the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device reset.
Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of
the transmit hardware for both channels are powered down to conserve
power. The GPWRDNT_[A:B] bit overrides the individual PWRDNT_xx
bits. GPWRDNT_[A:B] = 0 on device reset.
Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of
the receive hardware for both channels are powered down to conserve
power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx
bits. GPWRDNR_[A:B] = 0 on device reset.
Reserved, 1 on device reset.
Not used
Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and
receive sections of both channels are placed in test mode. The
GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits.
GTESTEN_[A:B] = 0 on device reset.
Test Mode - See Test Mode section for settings
Not used
Reserved
62
ORCA ORT42G5 and ORT82G5 Data Sheet
Description