ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 72

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Table 30. ORT82G5 Memory Map (Continued)
Lattice Semiconductor
30805 - Ax
30905 - Bx
30814 - Ax
30914 - Bx
Common Control Registers (Read/Write)
30A00
30A01
Absolute
Address
(0x)
[1] xC & xD
[4] xC & xD
xA & AB
xA & AB
[0]xA
[1]xB
[2]xC
[3]xD
[4]xA
[5]xB
[6]xC
[7]xD
[6:7]
[0:1]
[4:5]
[6:7]
[0:4]
[5:7]
[2:3
Bit
[0]
[2]
[3]
[5]
DEMUXWAS_xx
CH248_SYNC_xx
SYNC2_[A:B][1:2]
OVFL
SYNC4_
[A:B]OVFL
SYNC2_[A:B][1:2]
OOS
SYNC4_[A:B]_OO
S
Reserved for future use.
TCKSELA
RCKSELA
TCKSELB
RCKSELB
RX_FIFO_MIN
Name
—
Reset
Value
(0x)
00
00
00
00
Status of Word Alignment. When DEMUX_WAS_xx=1, word alignment is
achieved for Channel xx. DEMUX_WAS_xx=0 on device reset.
Status of Channel Alignment. When CH248_SYNC_xx=1, multi-channel
alignment is achieved for Channel xx. CH248_SYNC_xx=0 on device
reset.
Multi-Channel Overflow Status. When SYNC2_[A:B][1:2]OVFL=1, dual-
channel synchronization FIFO overflow has occurred.
SYNC2_[A:B][1:2]OVFL=0 on device reset.
Multi-Channel Overflow Status. When SYNC4_[A:B]OVFL=1, quad-
channel synchronization FIFO overflow has occurred.
SYNC4_[A:B]OVFL=0 on device reset.
Multi-Channel Out-Of-Sync Status. When SYNC2_[A:B][1:2] OOS=1,
dual-channel synchronization has failed.
SYNC2_[A:B][1:2] OOS=0 on device reset.
Multi-Channel Out-Of-Sync Status. When SYNC4_[A:B]_OOS=1, quad-
channel synchronization has failed.
SYNC4_[A:B]_OOS=0 on device reset.
Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES
quad A
00 = Channel AA
10 = Channel AB
01 = Channel AC
11 = Channel AD
Receive Clock Select. Controls source of 78 MHz RCK78 for SEDRES
quad A
00 = Channel AA
10 = Channel AB
01 = Channel AC
11 = Channel AD
Transmit Clock Select. Controls source of 78 MHz TCK78 for SERDES
quad B
00 = Channel BA
10 = Channel BB
01 = Channel BC
11 = Channel BD
Receive Clock Select. Controls source of 78 MHz RCK78 for SERDES
quad B
00 = Channel BA
10 = Channel BB
01 = Channel BC
11 = Channel BD
Reserved for future use
LSb’s for the threshold for low address in RX_FIFOs. RX_FIFO_MIN, Bit
5 is LSb. Useful values for RX_FIFO_MIN [0:4] are 0 to 17(decimal).
72
ORCA ORT42G5 and ORT82G5 Data Sheet
Description