pa28f004sc-120 Intel Corporation, pa28f004sc-120 Datasheet - Page 10

• Manufacturer Part Number: pa28f004sc-120
• Description: 8-mbit 1-mbit X 8 Flashfiletm Memory
• Manufacturer: Intel Corporation

28F008SA
Data Protection
Depending on the application the system designer
may choose to make the V
ble (available only when memory byte writes block
erases are required) or hardwired to V
V
The 28F008SA Command User Interface architec-
ture provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V
abled whenever V
age V
accommodates either design practice and encour-
ages optimization of the processor-memory inter-
face
The two-step byte write block erase Command User
Interface write sequence provides additional soft-
ware write protection
BUS OPERATION
Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles
Read
The 28F008SA has three read modes The memory
can be read from any of its blocks and information
can be read from the intelligent identifier or Status
Register V
NOTES
1 Refer to DC Characteristics When V
2 X can be V
voltages
3 RY BY
the WSM is not busy in Erase Suspend mode or deep powerdown mode
4 Command writes involving block erase or byte write are only successfully executed when V
5 Refer to Table 3 for valid D
10
Read
Output Disable
Standby
Deep PowerDown
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
PP
e
LKO
V
PPL
is V
PP
or when RP
IL
Mode
PP
or V
can be at either V
OL
memory contents cannot be altered
Additionally all functions are dis-
when the Write State Machine is executing internal block erase or byte write algorithms It is V
IH
CC
for control pins and addresses and V
is below the write lockout volt-
IN
is at V
PP
during a write operation
power supply switcha-
1 2 3 4 5
PPL
Notes
IL
1 2 3
1 2 3
1 2 3
PP
1 2
1 2
1 2
The 28F008SA
or V
e
V
PPH
PPH
PPL
Table 2 Bus Operations
RP
V
V
V
V
V
V
V
memory contents can be read but not written or erased
When
IH
IH
IH
IH
IH
IH
IL
CE
V
V
V
V
V
V
PPL
X
IH
IL
IL
IL
IL
IL
or V
The first task is to write the appropriate read mode
command to the Command User Interface (array in-
telligent
28F008SA automatically resets to Read Array mode
upon initial device powerup or after exit from deep
powerdown The 28F008SA has four control pins
two of which must be logically active to obtain data
at the outputs Chip Enable (CE ) is the device se-
lection control and when active enables the select-
ed memory device Output Enable (OE ) is the data
input output (DQ
active drives data from the selected memory onto
the I O bus RP
Figure 10 illustrates read bus cycle waveforms
Output Disable
With OE
puts are disabled Output pins (DQ
placed in a high-impedance state
Standby
CE
in standby mode Standby operation disables much
of the 28F008SA’s circuitry and substantially reduc-
es device power consumption The outputs (DQ
DQ
dent of the status of OE
lected during block erase or byte write the device
will continue functioning and consuming normal ac-
tive power until the operation completes
OE
PPH
7
V
V
V
V
V
) are placed in a high-impedence state indepen-
X
X
IH
IH
IL
IL
IL
at a logic-high level (V
for V
identifier
WE
at a logic-high level (V
PP
V
V
V
V
V
X
X
IH
IH
IH
IH
IL
See DC Characteristics for V
0
– DQ
V
V
A
and WE
X
X
X
X
X
IH
IL
0
or
7
) direction control and when
V
PP
X
X
X
X
X
X
X
PP
Status
If the 28F008SA is dese-
IH
e
) places the 28F008SA
must also be at V
V
DQ
High Z
High Z
High Z
PPH
D
A2H
IH
89H
D
OUT
) the device out-
IN
0–7
Register)
0
PPL
– DQ
RY BY
and V
V
V
V
OH
7
X
X
X
OH
OH
OH
X
) are
when
The
PPH
IH
0
–