km29w040ait Samsung Semiconductor, Inc., km29w040ait Datasheet - Page 11

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km29w040ait

Manufacturer Part Number
km29w040ait
Description
512k X 8 Bit Nand Flash Memory
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
I/O
Figure 3. Program Operation with CE don’ t -care.
I/O
KM29W040AT, KM29W040AIT
System Interface Using CE don’ t -care.
CLE
CE
WE
Figure 4. Read Operation with CE don’ t -care.
ALE
CE
WE
R/B
WE
CLE
ALE
CE
RE
0
0
~
~
7
7
t
CS
00H
80H
Start Add.(3Cycle)
Start Add.(3Cycle)
t
WP
t
CH
t
R
Data Input
11
I/O
CE
RE
0
~
Timing requirements : If CE is is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 60ns.
7
CE don’ t -care
(Max. 60ns)
CE don’ t -care
t
Data Output(sequential)
CEA
t
REA
FLASH MEMORY
Data Input
out
10H

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