k7i161882b Samsung Semiconductor, Inc., k7i161882b Datasheet - Page 12

• Manufacturer Part Number: k7i161882b
• Description: 512kx36-bit, 1mx18-bit Ddrii Cio B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7I163682B
K7I161882B
AC TIMING CHARACTERISTICS
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
Clock
Clock Cycle Time (K, K, C, C)
Clock Phase Jitter (K, K, C, C)
Clock High Time (K, K, C, C)
Clock Low Time (K, K, C, C)
Clock to Clock (K↑ → K↑, C↑ → C↑)
Clock to data clock (K↑ → C↑, K↑→ C↑)
DLL Lock Time (K, C)
K Static to DLL reset
Output Times
C, C High to Output Valid
C, C High to Output Hold
C, C High to Echo Clock Valid
C, C High to Echo Clock Hold
CQ, CQ High to Output Valid
CQ, CQ High to Output Hold
C, High to Output High-Z
C, High to Output Low-Z
Setup Times
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
2. Control signal are R and W.
The specs as shown do not imply bus contention because tCHQX
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
In case of BW
PARAMETER
0
,BW
1
(BW
2
, BW
3
SYMBOL
, also for x36) signal follow the data setup/hold times.
t
t
t
t
t
t
t
t
KC reset
t
t
t
CHCQV
CHCQX
CQHQV
CQHQX
t
t
t
KC lock
CHQX1
t
t
t
t
t
t
KC var
t
t
KHCH
CHQV
CHQX
CHQZ
KHKH
KHKH
AVKH
DVKH
KHAX
KHDX
KHKL
KLKH
IVKH
KHIX
(V
1024
-0.45
-0.45
-0.27
-0.45
DD
3.30
1.32
1.32
1.49
0.00
0.40
0.40
0.30
0.40
0.40
0.30
MIN
30
=1.8V±0.1V, T
-30
MAX
8.40
0.20
1.45
0.45
0.45
0.27
0.45
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
- 12 -
1
-0.45
-0.45
-0.30
-0.45
1024
MIN
4.00
1.60
1.60
1.80
0.00
0.50
0.50
0.35
0.50
0.50
0.35
is a MIN parameter that is worst case at totally different test conditions
30
1
A
is bigger than tCHQZ.
=0°C to +70°C)
-25
MAX
8.40
0.20
1.80
0.45
0.45
0.30
0.45
1024
-0.45
-0.45
-0.35
-0.45
5.00
2.00
2.00
2.20
0.00
0.60
0.60
0.40
0.60
0.60
0.40
MIN
30
-20
MAX
8.40
0.20
2.30
0.45
0.45
0.35
0.45
1024
-0.50
-0.50
-0.40
-0.50
6.00
2.40
2.40
2.70
0.00
0.70
0.70
0.50
0.70
0.70
0.50
MIN
Rev. 5.0 July 2006
30
-16
MAX
8.40
0.20
2.80
0.50
0.50
0.40
0.50
UNIT NOTE
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
3
3
7
7
3
3
2