k7i161882b Samsung Semiconductor, Inc., k7i161882b Datasheet - Page 14

• Manufacturer Part Number: k7i161882b
• Description: 512kx36-bit, 1mx18-bit Ddrii Cio B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

R/W
K7I163682B
K7I161882B
TIMING WAVE FORMS OF READ, WRITE AND NOP
LD
K
K
SA
DQ
C
C
CQ
CQ
1
NOP
NOTE
1. Q
2. Outputs are disabled(High-Z) one clock cycle after a NOP.
3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent
t
IVKH
bus contention.
t
KHCH
01
t
t
KLKH
refers to output from address A. Q
KHKL
READ
(burst of 2)
A
2
0
t
KHKH
t
KHIX
t
t
t
CHCQV
CHCQX
READ
(burst of 2)
CHQX1
A
3
t
1
CHQV
READ
(burst of 2)
A
4
Q
2
t
KHKH
01
Q
02
02
refers to output from the next internal burst address following A, etc.
NOP
5
Q
t
CHQX
11
Q
12
NOP
(Note3)
6
Q
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
21
- 14 -
Q
22
t
t
KHKH
KHKL
WRITE
(burst of 2)
A
7
3
t
DVKH
t
CHQZ
t
KHKH
(burst of 2)
WRITE
A
8
D
4
31
t
KLKH
t
CHCQX
D
32
t
KHDX
READ
(burst of 2)
9
A
D
5
41
t
D
CHCQV
42
(burst of 2)
READ
10
A
6
DON′T CARE
Rev. 5.0 July 2006
11
NOP
Q
51
t
CHQV
Q
52
UNDEFINED
NOP
12
Q
61
Q
62