k6r1016c1d Samsung Semiconductor, Inc., k6r1016c1d Datasheet
k6r1016c1d
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k6r1016c1d Summary of contents
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... K6R1016C1D Document Title 64Kx16 Bit High-Speed CMOS Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Rev. 0.0 Initial release with Preliminary. Rev. 0.1 Page 4, DC operation condition modify Rev. 0.2 Current modify Rev. 0.3 1. Delete 15ns speed bin. 2. Change Icc for Industrial mode. ...
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... K6R1016C1D 1Mb Async. Fast SRAM Ordering Information Org. Part Number K6R1004C1D-J(K)C(I) 10 256K x4 K6R1004V1D-J(K)C(I) 08/10 K6R1008C1D-J(K,T,U)C(I) 10 128K x8 K6R1008V1D-J(K,T,U)C(I) 08/10 K6R1016C1D-J(K,T,U,E)C(I) 10 64K x16 K6R1016V1D-J(K,T,U,E)C(I) 08/10 VDD(V) Speed ( ns ) PKG 32-SOJ K: 32-SOJ(LF) 3.3 8/ 32-SOJ K : 32-SOJ(LF 32-TSOP2 3.3 8/ 32-TSOP2(LF 44-SOJ K : 44-SOJ(LF 44-TSOP2 U : 44-TSOP2(LF) 3.3 8/ 48-TBGA - 2 - PRELIMINARY CMOS SRAM Temp. & Power ...
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... The K6R1016C1D is a 1,048,576-bit high-speed Static Random Access Memory organized as 65,536 words by 16 bits. The K6R1016C1D uses 16 common input and output lines and has at output enable pin which operates faster than address access time at read cycle. Also it allows that lower and upper byte access by data byte control (UB, LB). The device is fabricated using SAMSUNG′ ...
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... K6R1016C1D PIN CONFIGURATION(TOP VIEW SOJ/ I Vcc 11 TSOP2 Vss N.C 22 ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative ...
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... K6R1016C1D DC AND OPERATING CHARACTERISTICS* Parameter Symbol Input Leakage Current I LI Output Leakage Current I LO Operating Current I CC Standby Current SB1 Output Low Voltage Level V OL Output High Voltage Level The above parameters are also guaranteed at industrial temperature range. CAPACITANCE* (T =25° ...
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... OLZ t 0 BLZ OHZ t 0 BHZ K6R1016C1D-10 Min WP1 WHZ (Address Controlled CS=OE PRELIMINARY CMOS SRAM ...
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... K6R1016C1D TIMING WAVEFORM OF READ CYCLE(2) Address CS UB Data out High Current SB NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...
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... K6R1016C1D TIMING WAVEFORM OF WRITE CYCLE(2) Address CS UB Data in Data out TIMING WAVEFORM OF WRITE CYCLE(3) Address CS UB High-Z Data in High-Z Data out (OE =Low fixed CW( WP1(2) AS(4) High-Z t WHZ(6) (CS=Controlled CW( WP(2) AS( WHZ( PRELIMINARY ...
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... K6R1016C1D TIMING WAVEFORM OF WRITE CYCLE(4) Address CS UB High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS, WE, LB and UB. A write begins at the latest transition CS going low and WE going low ...
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... K6R1016C1D PACKAGE DIMENSIONS 44-SOJ-400 #44 11.18 ±0.12 0.440 ±0.005 #1 +0.10 0.43 -0.05 0.017 +0.004 0. -0.002 0.0375 44-TSOP2-400BF #44 #1 18.81 0.741 18.41 0.725 +0.10 0.30 0.805 −0. +0.004 0.012 0.032 −0.002 28.98 MAX 1.141 25.58 ±0.12 1.125 ±0.005 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 #23 11.76 0.463 #22 MAX ±0.10 ±0.004 1.00 ±0.10 0.039 0.05 MIN ...
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... K6R1016C1D PACKAGE DIMENSION 48 TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View B #A1 Side View D Min A - 0.75 B 5.90 6. 3.75 C 6.90 7. 5.25 D 0.40 0.45 E 0.80 0. 0.55 E2 0.30 0. Typ Max - 6.10 - 7.10 - 0.50 1.00 - 0. PRELIMINARY CMOS SRAM Bottom View B/2 Detail Notes. 1. Bump counts: 48(8 row x 6 column) 2 ...