qh25f320s33b8 Numonyx, qh25f320s33b8 Datasheet - Page 31

• Manufacturer Part Number: qh25f320s33b8
• Description: Numonyx? Serial Flash Memory S33
• Manufacturer: Numonyx

Numonyx™ Serial Flash Memory (S33)
Table 16: Status Register Bit Definition
8.3.1
December 2007
Order Number: 314822-03
Notes:
1.
2.
3.
Bit
SR
7
6
5
4
3
2
1
0
P_FAIL
E_FAIL
Name
SRWD
Refer to
The Program and Erase Fail flags are not directly writable, but they can be reset with the Clear SR Fail Flag command.
This is true regardless of the protection modes described in
The WEL bit is not directly writable but it can be set with the Write Enable command and reset with the Write Disable
command. This is true regardless of the protection modes described in
WEL
BP2
BP1
BP0
WIP
Bit
Table 18, “Main Array Protection Modes” on page 32
Main Memory Protection
Main memory program/erase protection is defined by three Status Register bits
(SR[4:2]) and the W# input signal.
Table 18
Hardware Protection Mode.
Status Register Write Disable - When this writeable bit is set and W# is low,
none of the writable SR bits can be changed including these bits (that is, SR7,
4:2). For details, refer to
on page 32
Program Fail Flag - When set, this bit indicates that a program failure
occurred. This bit will also be set when the user attempts to program a
protected main memory region or a locked OTP region.
However, the Program Fail Flag will not be set under the following scenarios:
After a series of program operations, this bit indicates whether one or more of
these operations failed. Once set, this bit is reset with the Clear SR Fail Flag
command.
Erase Fail Flag - When set, this bit indicates that an erase failure occurred.
This bit will also be set when the user attempts to erase a protected main
memory region.
However, the Erase Fail Flag will not be set under the following scenarios:
After a series of erase operations, this bit indicates whether one or more of the
operations failed. Once set, this bit is reset with the Clear SR Fail Flag
command.
Sector Protect Bits - These bits define the lock region of the main memory. A
locked region is one or more adjacent memory sectors that are protected from
program or erase. For further details, refer to
these bits are “0”, the entire main array is unlocked. These bits are volatile; at
power-up, these bits are set to “1”.
Write Enable Latch - This bit must be set prior to the following SPI
Commands:
After issuing one of these commands, the WEL bit will clear when the command
is completed. The WEL bit will not be cleared if the command is botched by not
raising S# on a whole-byte increment.
Write in Process - When a program, erase, or write to the SR is in process
(busy), the WIP reads as “1”. When the WIP bit is zero, the SPI interface is in
its ready state.
• Botched Command Sequence (that is, S# edge not raised on a whole-byte
• Write Enable Latch bit is reset (that is, SR1 = 0)
• Botched Command Sequence (that is, S# edge not raised on a whole-byte
• Write Enable Latch bit is reset (that is, SR1 = 0)
• Write SPI SR
• Page Program
• OTP Program
• Bulk Erase
• Parameter Block Erase
• Sector Erase
increment)
increment).
defines the SR and W# configurations for Software Protection Mode and
. This bit is volatile.
Table 18, “Main Array Protection Modes”
Bit Description
Table 17
Table 17
Table 18
defines the memory protection regions.
. When all three of
.
Table 18
for writable conditions.
.
Power-
State
up
0
0
0
1
1
1
0
0
Read/Write
Read/Write
Read/Write
Read/Write
Write/Read
Read only
Read only
read only
Capability
read only
Datasheet
(3)
(2)
(2)
(1)
(1)
(1)
(1)
31