cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 16

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

Table 1-1.
29380-DSH-001-B
RLOS [1:4]
LLOOP [1:4]
RLOOP [1:4]
TDO
TDI
TMS
TCK
TRST
CS
SDI
SDO
SCLK
VAA
GND
VAAT[1:4]
GNDT[1:4]
VAAR
GNDR
VAACL
GNDCL
Pin Label
Hardware Signal Definitions (4 of 5)
Receive Loss of
Signal
Local Loop
Remote Loop
Test Data Output
Test Data Input
Test Mode Select
Test Clock
Reset
Chip Select
Serial Data In
Serial Data Out
Serial Clock
Analog Supply
Ground
Tx Driver Supply
Ground
Rx Analog Supply
Ground
CLAD Supply
Ground
Signal Name
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
Power Supply Pins and No-Connect Pins
O
I
I
I
I
P
P
P
P
I/O
O
I
I
I
I
O
I
I
I
I
I
P
P
P
P
P
Boundary Scan Signals (JTAG)
Host Serial Control Signals
RLOS is asserted low when 100 (T1) or 32 (E1) consecutive 0s (no pulses) are
received at the line interface or when the received signal level is below RALOS
threshold nominal for at least 1 ms (see
These pins are always enabled in Hardware Mode and may be enabled or disabled
in Host Mode [LIU_CTL; addr n3]. A low on LLOOP initiates Local Analog
Loopback and a low on RLOOP initiates Remote Line Loopback. Local Digital
Loopback is initiated if both signals are asserted together.
Test data output per IEEE Std. 1149.1-1990. Three-state output used for reading
all serial configuration and test data from internal test logic. Updated on the falling
edge of TCK.
Test data input per IEEE Std. 1149.1-1990. Used for loading all serial instructions
and data into internal test logic. Sampled on the rising edge of TCK. TDI may be
left unconnected if not used.
Active-low test mode select input per IEEE Std 1149.1-1990. Internally pulled-up
input signal used to control the test logic state machine. Sampled on the rising
edge of TCK. TMS may be left unconnected if not used.
Test clock input per IEEE Std. 1149.1-1990. Used for all test interface and internal
test-logic operations. If not used, TCK should be pulled low.
Active low reset. TRST is pulled up internally and may be left unconnected if not
used.
In Host Mode, CS is an active low input used to enable read/write access with the
host serial control port. CS /JSEL(1) is a dual function pin.
In Host Mode, SDI is the serial data input for the host serial control port. SDI/
JSEL(2) is a dual function pin.
In Host Mode, SDO is the serial data output for the host serial control port. SDO/
JATERR[1] is a dual function pin.
In Host Mode, SCLK is the serial clock input for the host serial control port. SCLK/
JDIR is a dual function pin.
+3.3 V ± 5%. Power supply pair for the analog circuitry.
+3.3 V ± 5%. Power supply pairs for the transmitter driver circuitry. These pin
pairs should each be bypassed with a tantalum capacitor value of at least 10
+3.3 V ± 5%. Power supply pair for the analog receiver circuitry.
+3.3 V ± 5%. Power supply pair for the CLAD PLL circuitry.
®
Definition
Table
2-1).
Pin Descriptions
µ
F.
8