cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 27

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

meets jitter tolerance tests defined in ETS 300 011: ISDN; Primary Rate User-Network Interface Layer 1
Specification and Test Principles.
2.3.4
The data slicer outputs can be routed to the JAT before going to the RZCS decoder. The JAT attenuates clock and
data jitter introduced by the line or added by the clock recovery circuit. The JAT can be placed in the receive path or
transmit path, but not in both simultaneously. If the JAT is placed in the receive path, RCKO is replaced with the
jitter attenuated clock. The JAT performance is discussed in
In Host Mode, the JAT is configured for each channel independently and is put in the receive path by setting JEN
and JDIR register bits to 1 [JAT_CR; addr n0]. In Hardware Mode, the JAT is configured for all channels globally
using the JSEL(2:0) and JDIR pins. See
2.3.5
The RZCS decoder decodes the dual-rail data from the data slicer or from the JAT. In T1 mode, the RZCS decoder
replaces received B8ZS codes with eight 0s. In E1 mode, HDB3 codes are replaced with four 0s. The B8ZS code is
000VB0VB and the HDB3 code is X00V; where B is a normal AMI pulse, V is a bipolar violation, and X is a Don't
Care.
ZCS decoding (and encoding) can be enabled only if the digital interface mode is unipolar. In Host Mode, RZCS
decoding (and TZCS encoding) is enabled for each channel by setting the ZCS [RLIU_CR; addr n1] register bit to
1. In Hardware Mode, ZCS encoding/decoding is controlled globally for all channels by pulling the ZCS pin high.
For the Hardware Mode pin definition, see
2.3.6
The digital receiver outputs are provided on the RPOSO[n], RNEGO[n], and RCKO[n] pins, where [n] is channel
number 1 to 4. The receiver outputs can be configured to operate in two modes: bipolar NRZ format or unipolar
NRZ format. In both modes, RPOSO[n] and RNEGO[n] outputs are clocked by RCKO[n], the recovered line rate
clock, or the jitter attenuated clock if the JAT is enabled in the receive path. RCKO[n] polarity is configurable by the
CLK_POL pin in Hardware Mode or register bit CLK_POL [RLIU_CR; addr n1] in Host Mode. RPOSO[n],
RNEGO[n], and RCKO[n] are three-stated during device reset.
2.3.6.1
In bipolar mode, RPOSO/RNEGO signals output received data in bipolar dual-rail format, where a high level on
RPOSO indicates receipt of a positive AMI pulse, and a high level on RNEGO indicates receipt of a negative AMI
pulse on RTIP/RING inputs. In bipolar mode, the RZCS decoder is not available. In Hardware Mode, bipolar
operation is enabled globally for all channels by pulling the UNIPOLAR pin high. In Host Mode, bipolar operation is
enabled per channel by writing a 0 to register bit UNIPOLAR [RLIU_CR; addr n1].
2.3.6.2
In unipolar mode, RPOSO/RNEGO signals are replaced by RDATO/BPV signals. AMI encoded received data is
decoded and output on RDATO in NRZ format, and BPV indicates that the currently received bit is a bipolar
violation. If the RZCS decoder is enabled, the BPV pin indicates only bipolar violations which are not part of a ZCS
code (B8ZS or HDB3). In Hardware Mode, unipolar operation is enabled by pulling the UNIPOLAR pin low. In Host
Mode, unipolar operation is enabled by writing a 1 to register bit UNIPOLAR [RLIU_CR; addr n1].
29380-DSH-001-B
Receive Jitter Attenuator
RZCS Decoder
Receive Digital Interface
Bipolar Mode
Unipolar Mode
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
Chapter 1
Table
1-1.
for details.
Section
®
2.6.
Circuit Description
19