cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 22

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

2.2.4.1
An internal power-on reset process is initiated during power-up. When VDD has reached approximately 2.6 V, the
internal reset process begins and continues for 300 ms maximum if REFCLK is applied. If REFCLK is not present,
the CX28380 remains in the reset state.
2.2.4.2
Hard reset is initiated by bringing the RESET pin active (low). Once initiated, the internal reset process completes
in 5 µs maximum. If the RESET pin is held active continuously, the clock and data outputs and the IRQ pin remain
three-stated. The following output pins are forced to high impedance while RESET is held active:
RLOS[1:4] are forced high and JATERR[1] is forced low.
2.2.4.3
In Host Mode, soft reset is initiated by writing a one to the RESET bit in the Global Configuration register [addr 01].
The RESET bit is self-clearing. Once initiated, the internal reset process completes in 5 µs maximum and the
device enters normal operation.
29380-DSH-001-B
RPOSO[1:4]
RNEGO[1:4]
RCKO[1:4]
XTIP[1:4]
XRING[1:4]
CLK1544
Power-on Reset
Hard Reset
Soft Reset
CLADO
TCLK[1:4]
CLK2048
JATERR[2:4]
SDO
IRQ
Preliminary Information / Mindspeed Proprietary and Confidential
Transmitter clocks, TCLK[1:4], are configured
as inputs.
The
IRQ
Mindspeed Technologies
pin is enabled (controlled by DPM).
Hardware Mode
®
Transmitter clocks, TCLK[1:4], are configured as
inputs.
The
All interrupt sources are disabled.
All configuration registers are set to default
values as listed in
IRQ
pin is three-stated.
Host Mode
Section
3.1.
Circuit Description
14