cx28224 Mindspeed Technologies, cx28224 Datasheet - Page 158

• Manufacturer Part Number: cx28224
• Description: Cx28224/5/9 Inverse Multiplexing For The Atm Ima Family
• Manufacturer: Mindspeed Technologies

Registers
7-58
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0x32—IDLCNTH (Idle Cell Receive Counter [High Byte])
0x33—LOCDCNT (LOCD Event Counter)
IdleCnt[18]
IdleCnt[17]
IdleCnt[16]
LOCDCnt[7]
LOCDCnt[6]
LOCDCnt[5]
LOCDCnt[4]
LOCDCnt[3]
LOCDCnt[2]
LOCDCnt[1]
LOCDCnt[0]
The IDLCNTH counter tracks the number of received cells. The counter is cleared on
read.
This counter tracks the number of times that cell delineation was lost. Note that the
LOCD interrupt is a dual event interrupt and is set when cell delineation is lost or
regained. Thus the number of LOCD events will not match the number of LOCD
interrupts.
Name
Name
—
—
—
—
—
Mindspeed Technologies
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Received cell counter bit 18 (MSB).
Received cell counter bit 17.
Received cell counter bit 16.
LOCD Event counter bit 7 (MSB).
LOCD Event counter bit 6.
LOCD Event counter bit 5.
LOCD Event counter bit 4.
LOCD Event counter bit 3.
LOCD Event counter bit 2.
LOCD Event counter bit 1.
LOCD Event counter bit 0 (LSB).
Description
Description
™
CX28224/5/9 Data Sheet
28229-DSH-001-D