k7a803601m Samsung Semiconductor, Inc., k7a803601m Datasheet
k7a803601m
Related parts for k7a803601m
k7a803601m Summary of contents
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... K7A803601M K7A801801M Document Title 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History 0.0 Initial draft 0.1 Modify DC characteristics( Input Leakage Current test Conditions) form Max 0.2 Remove 119BGA Package Type. 0.3 Change DC Characteristics. I value from 65mA to 110mA at - value from 60mA to 110mA at -85 ...
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... LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by cur- rent regardless of CLK. -10 Unit The K7A803601M and K7A801801M are fabricated using SAM- SUNG s high performance CMOS technology and is available 100pin TQFP package. Multiple power and ground pins are 4 ...
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... The pin 42 is reserved for address bit for the 16Mb . 256Kx36 & 512Kx18 Synchronous SRAM 100 Pin TQFP (20mm x 14mm) K7A803601M(256Kx36) TQFP PIN NO. SYMBOL PIN NAME 32,33,34,35,36,37,43 V Power Supply(+3.3V) ...
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... K7A803601M K7A801801M PIN CONFIGURATION (TOP VIEW) N.C. 1 N. DDQ V 5 SSQ 6 N.C. 7 N.C. DQb 8 0 DQb SSQ V 11 DDQ DQb 12 2 DQb DQb 18 4 DQb DDQ V 21 SSQ DQb 22 6 DQb 23 7 DQPb 24 N ...
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... K7A801801M FUNCTION DESCRIPTION The K7A803601M and K7A801801M are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. ...
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... K7A803601M K7A801801M TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADSP ADSC ADV ...
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... K7A803601M K7A801801M PASS-THROUGH TRUTH TABLE PREVIOUS CYCLE OPERATION WRITE Write Cycle, All bytes All L Address=An-1, Data=Dn-1 Write Cycle, All bytes All L Address=An-1, Data=Dn-1 Write Cycle, All bytes All L Address=An-1, Data=Dn-1 Write Cycle, One byte One L Address=An-1, Data=Dn-1 Write Cycle, One byte ...
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... K7A803601M K7A801801M DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ Output Leakage Current I OL Operating Current Standby Current I SB1 I SB2 Output Low Voltage(3.3V I/ Output High Voltage(3.3V I/ Output Low Voltage(2.5V I/ Output High Voltage(2.5V I/ Input Low Voltage(3.3V I/O) ...
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... K7A803601M K7A801801M Output Load(A) Dout Zo=50 AC TIMING CHARACTERISTICS PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 10 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 11 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 12 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 13 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M 256Kx36 & 512Kx18 Synchronous SRAM - 14 - May 1999 Rev 3.0 ...
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... K7A803601M K7A801801M APPLICATION INFORMATION DEPTH EXPANSION The Samsung 256Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic. Data Address A [0:18] CLK Microprocessor CLK ...
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... K7A803601M K7A801801M APPLICATION INFORMATION DEPTH EXPANSION The Samsung 512Kx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. Data Address A [0:19] CLK Microprocessor CLK ...
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... K7A803601M K7A801801M PACKAGE DIMENSIONS 100-TQFP-1420A 22.00 20.00 #1 0.65 256Kx36 & 512Kx18 Synchronous SRAM 0.30 0.20 16.00 0.30 14.00 0.20 (0.83) (0.58) 0.30 0.10 0.10 MAX 1.40 1.60 MAX 0.10 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 0.10 MAX 0.50 0.10 May 1999 Rev 3.0 ...